XC3S100E_06 Datasheet, PDF (154/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

R
DC and Switching Characteristics
Serial Peripheral Interface (SPI) Configuration Timing
PROG_B
(Input)
HSWAP
(Input)
VS[2:0]
(Input)
M[2:0]
(Input)
INIT_B
(Open-Drain)
HSWAP must be stable before INIT_B goes High and constant throughout the configuration process.
<1:1:1>
T_MINIT
<0:0:1>
T_INITM
Mode input pins M[2:0] and variant select input pins VS[2:0] are sampled when INIT_B
goes High. After this point, input values do not matter until DONE goes High, at which
point these pins become user-I/O pins.
New ConfigRate active
CCLK
T_CCLK1
T_MCCL1 T_MCCH1
T_MCCLn
T_CCLK1
T_CCLKn
T_MCCHn
DIN
(Input)
CSO_B
MOSI
T_V
T_CSS
T_CCO
Command
(msb)
Command
(msb-1)
T_DSU
T_DH
Data
Data
T_DCC
Data
T_CCD
Pin initially pulled High by internal pull-up resistor if HSWAP input is Low.
Pin initially high-impedance (Hi-Z) if HSWAP input is High. External pull-up resistor required on CSO_B.
Data
Shaded values indicate specifications on attached SPI Flash PROM.
Figure 77: Waveforms for Serial Peripheral Interface (SPI) Configuration
ds312-3_06_110206
Table 117: Timing for Serial Peripheral Interface (SPI) Configuration Mode
Symbol
Description
T_CCLK1
T_CCLKn
T_MINIT
Initial CCLK clock period
CCLK clock period after FPGA loads ConfigRate setting
Setup time on VS[2:0] and M[2:0] mode pins before the rising
edge of INIT_B
T_INITM
Hold time on VS[2:0] and M[2:0]mode pins after the rising edge of
INIT_B
T_CCO
T_DCC
T_CCD
MOSI output valid after CCLK edge
Setup time on DIN data input before CCLK edge
Hold time on DIN data input after CCLK edge
Minimum Maximum
(see Table 111)
(see Table 111)
50
-
0
-
See Table 115
See Table 115
See Table 115
Units
ns
ns
154
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DS312-3 (v3.4) November 9, 2006
Product Specification