XC3S100E_06 Datasheet, PDF (59/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

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Functional Description
Stabilizing DCM Clocks Before User Mode
The STARTUP_WAIT attribute shown in Table 39 optionally
delays the end of the FPGA’s configuration process until
after the DCM locks to its incoming clock frequency. This
option ensures that the FPGA remains in the Startup phase
of configuration until all clock outputs generated by the
DCM are stable. When all DCMs that have their
STARTUP_WAIT attribute set to TRUE assert the LOCKED
signal, then the FPGA completes its configuration process
and proceeds to user mode. The associated bitstream gen-
erator (BitGen) option LCK_cycle specifies one of the six
cycles in the Startup phase. The selected cycle defines the
point at which configuration stalls until all the LOCKED out-
puts go High. See Start-Up, page 107 for more information.
Table 39: STARTUP_WAIT Attribute
Attribute
Description
Values
STARTUP_WAIT
When TRUE,
delays transition
from configuration
to user mode until
DCM locks to the
input clock.
TRUE, FALSE
Clocking Infrastructure
The Spartan-3E clocking infrastructure, shown in Figure 45,
provides a series of low-capacitance, low-skew interconnect
lines well-suited to carrying high-frequency signals through-
out the FPGA. The infrastructure also includes the clock
inputs and BUFGMUX clock buffers/multiplexers. The Xilinx
Place-and-Route (PAR) software automatically routes
high-fanout clock signals using these resources.
Clock Inputs
Clock pins accept external clock signals and connect directly
to DCMs and BUFGMUX elements. Each Spartan-3E FPGA
has:
• 16 Global Clock inputs (GCLK0 through GCLK15)
located along the top and bottom edges of the FPGA
• 8 Right-Half Clock inputs (RHCLK0 through RHCLK7)
located along the right edge
• 8 Left-Half Clock inputs (LHCLK0 through LHCLK7)
located along the left edge
DESIGN NOTE:
! ^{Avoid using global clock input GCLK1 as it is always}
shared with the M2 mode select pin. Global clock
inputs GCLK0, GCLK2, GCLK3, GCLK12, GCLK13,
GCLK14, and GCLK15 have shared functionality in
some configuration modes.
Clock inputs optionally connect directly to DCMs using ded-
icated connections. Table 30, Table 31, and Table 32 show
the clock inputs that best feed a specific DCM within a given
Spartan-3E part number. Different Spartan-3E FPGA densi-
ties have different numbers of DCMs. The XC3S1200E and
XC3S1600E are the only two densities with the left- and
right-edge DCMs.
Each clock input is also optionally a user-I/O pin and con-
nects to internal interconnect. Some clock pad pins are
input-only pins as indicated in Pinout Descriptions (Mod-
ule 4).
Clock Buffers/Multiplexers
Clock Buffers/Multiplexers either drive clock input signals directly onto
a clock line (BUFG) or optionally provide a multiplexer to switch
between two unrelated, possibly asynchronous clock signals (BUFG-
MUX).
Each BUFGMUX element, shown in Figure 46, is a 2-to-1 multiplexer.
The select line, S, chooses which of the two inputs, I0 or I1, drives the
BUFGMUX’s output signal, O, as described in Table 40. The switching
from one clock to the other is glitch-less, and done in such a way that
the output High and Low times are never shorter than the shortest
High or Low time of either input clock. The two clock inputs can be
asynchronous with regard to each other, and the S input can change
at any time, except for a short setup time prior to the rising edge of the
presently selected clock (I0 or I1). This setup time is specified as T_GSI
in Table 100, page 140. Violating this setup time requirement possibly
results in an undefined runt pulse output.
Table 40: BUFGMUX Select Mechanism
S Input
O Output
0
I0 Input
1
I1 Input
The BUFG clock buffer primitive drives a single clock signal onto the
clock network and is essentially the same element as a BUFGMUX,
just without the clock select mechanism. Similarly, the BUFGCE prim-
itive creates an enabled clock buffer using the BUFGMUX select
mechanism.
The I0 and I1 inputs to an BUFGMUX element originate from clock
input pins, DCMs, or Double-Line interconnect, as shown in Figure 46.
As shown in Figure 45, there are 24 BUFGMUX elements distributed
around the four edges of the device. Clock signals from the four BUF-
GMUX elements at the top edge and the four at the bottom edge are
truly global and connect to all clocking quadrants. The eight left-edge
BUFGMUX elements only connect to the two clock quadrants in the
left half of the device. Similarly, the eight right-edge BUFGMUX ele-
ments only connect to the right half of the device.
BUFGMUX elements are organized in pairs and share I0 and I1 con-
nections with adjacent BUFGMUX elements from a common clock
switch matrix as shown in Figure 46. For example, the input on I0 of
one BUFGMUX is also a shared input to I1 of the adjacent BUFGMUX.
The clock switch matrix for the left- and right-edge BUFGMUX ele-
ments receive signals from any of the three following sources: an
LHCLK or RHCLK pin as appropriate, a Double-Line interconnect, or a
DCM in the XC3S1200E and XC3S1600E devices.
DS312-2 (v3.4) November 9, 2006
www.xilinx.com
59
Product Specification