XC3S100E_06 Datasheet, PDF (1/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

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Spartan-3E FPGA Family:
Complete Data Sheet
DS312 November 9, 2006
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Module 1:
Introduction and Ordering Information
DS312-1 (v3.4) November 9, 2006
• Introduction
• Features
• Architectural Overview
• Package Marking
• Ordering Information
Module 2:
Functional Description
DS312-2 (v3.4) November 9, 2006
• Input/Output Blocks (IOBs)
- Overview
- SelectIO™ Signal Standards
• Configurable Logic Block (CLB)
• Block RAM
• Dedicated Multipliers
• Digital Clock Manager (DCM)
• Clock Network
• Configuration
• Powering Spartan-3E FPGAs
• Production Stepping
Module 3:
DC and Switching Characteristics
DS312-3 (v3.4) November 9, 2006
• DC Electrical Characteristics
- Absolute Maximum Ratings
- Supply Voltage Specifications
- Recommended Operating Conditions
- DC Characteristics
• Switching Characteristics
- I/O Timing
- SLICE Timing
- DCM Timing
- Block RAM Timing
- Multiplier Timing
- Configuration and JTAG Timing
Module 4:
Pinout Descriptions
DS312-4 (v3.4) November 9, 2006
• Pin Descriptions
• Package Overview
• Pinout Tables
• Footprint Diagrams
© 2005-2006 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc.
All other trademarks are the property of their respective owners.
DS312 November 9, 2006
www.xilinx.com
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