XC3S100E_06 Datasheet, PDF (108/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

Functional Description
R
The relative timing of configuration events is programmed
via the Bitstream Generator (BitGen) options in the Xilinx
development software. For example, the GTS and GWE
events can be programmed to wait for all the DONE pins to
High on all the devices in a multiple-FPGA daisy-chain,
forcing the FPGAs to start synchronously. Similarly, the
start-up sequence can be paused at any stage, waiting for
selected DCMs to lock to their respective input clock sig-
nals. See also Stabilizing DCM Clocks Before User
Mode.
By default, the start-up sequence is synchronized to CCLK.
Alternatively, the start-up sequence can be synchronized to
a user-specified clock from within the FPGA application
using the STARTUP_SPARTAN3E library primitive and by
setting the StartupClk bitstream generator option. The
FPGA application can optionally assert the GSR and GTS
signals via the STARTUP_SPARTAN3E primitive. For
JTAG configuration, the start-up sequence can be synchro-
nized to the TCK clock input.
Readback
FPGA configuration data can be read back using either the
Slave Parallel or JTAG mode. This function is disabled if the
Bitstream Generator Security option is set to either Level1
or Level2.
Along with the configuration data, it is possible to read back
the contents of all registers and distributed RAM.
To synchronously control when register values are captured
for readback, use the CAPTURE_SPARTAN3 library primi-
tive, which applies for both Spartan-3 and Spartan-3E
FPGA families.
The Readback feature is available in most Spartan-3E
FPGA product options, as indicated in Table 67. The Read-
back feature is not available in the XC3S1200E and
XC3S1600E FPGAs when using the -4 speed grade in the
Commercial temperature grade. Similarly, block RAM
Readback support is not available in the -4 speed grade,
Commercial temperature devices. If Readback is required
in an XC3S1200E or XC3S1600E FPGA, or if block RAM
Readback is required on any Spartan-3E FPGA, upgrade to
either the Industrial temperature grade version or the -5
speed grade.
The Xilinx iMPACT programming software uses the Read-
back feature for its optional Verify and Readback opera-
tions. The Xilinx ChipScope™ software presently does not
use Readback but may in future updates.
Table 67: Readback Support in Spartan-3E FPGAs
Temperature Range
Commercial
Industrial
Speed Grade -4
-5
-4
Block RAM Readback
All Spartan-3E No
Yes
Yes
FPGAs
General Readback (registers, distributed RAM)
XC3S100E Yes
Yes
Yes
XC3S250E Yes
Yes
Yes
XC3S500E Yes
Yes
Yes
XC3S1200E No
Yes
Yes
XC3S1600E No
Yes
Yes
Bitstream Generator (BitGen) Options
Various Spartan-3E FPGA functions are controlled by spe-
cific bits in the configuration bitstream image. These values
are specified when creating the bitstream image with the
Bitstream Generator (BitGen) software.
Table 68 provides a list of all BitGen options for Spartan-3E
FPGAs.
Table 68: Spartan-3E FPGA Bitstream Generator (BitGen) Options
Option Name
Pins/Function
Affected
Values
(default)
Description
ConfigRate
CCLK,
Configuration
1, 3, 6,
12, 25, 50
Sets the approximate frequency, in MHz, of the internal oscillator using for Master
Serial, SPI, and BPI configuration modes. The internal oscillator powers up at its lowest
frequency, and the new setting is loaded as part of the configuration bitstream. The
software default value is 1 (~1.5 MHz) starting with ISE 8.1, Service Pack 1.
StartupClk
Configuration,
Startup
Cclk
Default. The CCLK signal (internally or externally generated) controls the startup
sequence when the FPGA transitions from configuration mode to the user mode. See
Start-Up.
UserClk
A clock signal from within the FPGA application controls the startup sequence when
the FPGA transitions from configuration mode to the user mode. See Start-Up. The
FPGA application supplies the user clock on the CLK pin on the
STARTUP_SPARTAN3E primitive.
Jtag The JTAG TCK input controls the startup sequence when the FPGA transitions from
the configuration mode to the user mode. See Start-Up.
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DS312-2 (v3.4) November 9, 2006
Product Specification