XC3S100E_06 Datasheet, PDF (147/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

R
DC and Switching Characteristics
Table 106: Switching Characteristics for the DFS (Continued)
Symbol
Lock Time
LOCK_FX⁽²⁾
Description
Device
The time from deassertion at the
5 MHz < F_CLKIN
All
DCM’s Reset input to the rising
< 15 MHz
transition at its LOCKED output. The
DFS asserts LOCKED when the
CLKFX and CLKFX180 signals are
F_CLKIN >
15 MHz
valid. If using both the DLL and the
DFS, use the longer locking time.
Speed Grade
-5
-4
Min Max Min Max
Units
-
5
-
5
ms
-
450
-
450
μs
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 76 and Table 105.
2. For optimal jitter tolerance and faster lock time, use the CLKIN_PERIOD attribute.
3. Use the Virtex-II Jitter Calculator at http://www.xilinx.com/applications/web_ds_v2/jitter_calc.htm.or the jitter calculator included in
Clock Wizard/DCM Wizard. Output jitter includes 150 ps of input clock jitter.
4. The CLKFX and CLKFX180 outputs always have an approximate 50% duty cycle.
5. Some duty-cycle and alignment specifications include 1% of the CLKFX output period or 0.01 UI. Example: The data sheet specifies
a maximum jitter of "±[1% of CLKFX period + 300]". Assume the CLKFX output frequency is 100 MHz. The equivalent CLKFX period
is 10 ns and 1% of 10 ns is 0.1 ns or 100 ps. According to the data sheet, the maximum jitter is ±[100 ps + 300 ps] = ±400 ps.
Phase Shifter (PS)
Table 107: Recommended Operating Conditions for the PS in Variable Phase Mode
Speed Grade
-5
-4
Symbol
Description
Min
Max
Min
Max
Operating Frequency Ranges
PSCLK_FREQ
(F_PSCLK)
Frequency for the PSCLK input
Input Pulse Requirements
1
167
1
167
PSCLK_PULSE PSCLK pulse width as a percentage of the PSCLK period
40% 60% 40% 60%
Units
MHz
-
Table 108: Switching Characteristics for the PS in Variable Phase Mode
Symbol
Description
Phase Shifting Range
MAX_STEPS⁽²⁾
Maximum allowed number of DCM_DELAY_STEP
steps for a given CLKIN clock period, where T = CLKIN
clock period in ns. If using
CLKIN_DIVIDE_BY_2 = TRUE, double the clock
effective clock period.
FINE_SHIFT_RANGE_MIN Minimum guaranteed delay for variable phase shifting
FINE_SHIFT_RANGE_MAX Maximum guaranteed delay for variable phase shifting
±[INTEGER(20 • (T_CLKIN – 3 ns))]
±[MAX_STEPS •
DCM_DELAY_STEP_MIN]
±[MAX_STEPS •
DCM_DELAY_STEP_MAX]
Units
steps
ns
ns
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 76 and Table 107.
2. The maximum variable phase shift range, MAX_STEPS, is only valid when the DCM is has no initial fixed phase shifting, i.e., the PHASE_SHIFT
attribute is set to 0.
3. The DCM_DELAY_STEP values are provided at the bottom of Table 104.
DS312-3 (v3.4) November 9, 2006
www.xilinx.com
147
Product Specification