XC3S100E_06 Datasheet, PDF (137/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

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Table 96: Recommended Number of Simultaneously
Switching Outputs per V_CCO-GND Pair
Package Type
Signal Standard
(IOSTANDARD)
FT256,
FG320,
VQ TQ PQ CP FG400,
100 144 208 132 FG484
Single-Ended Standards
LVTTL
Slow 2 34
20
19
52
60
4 17
10
10
26
41
6 17
10
7
26
29
88
6
6
13
22
12 8
6
5
13
13
16 5
5
5
6
11
Fast 2 17
17
17
26
34
49
9
9
13
20
67
7
7
13
15
86
6
6
6
12
12 5
5
5
6
10
16 5
5
5
5
9
LVCMOS33 Slow 2 34
20
20
52
76
4 17
10
10
26
46
6 17
10
7
26
27
88
6
6
13
20
12 8
6
5
13
13
16 5
5
5
6
10
Fast 2 17
17
17
26
44
48
8
8
13
26
68
6
6
13
16
86
6
6
6
12
12 5
5
5
6
10
16 8
8
5
5
8
LVCMOS25 Slow 2 28
16
16
42
76
4 13
10
10
19
46
6 13
7
7
19
33
86
6
6
9
24
12 6
6
6
9
18
Fast 2 17
16
16
26
42
49
9
9
13
20
69
7
7
13
15
86
6
6
6
13
12 5
5
5
6
11
LVCMOS18 Slow 2 19
11
8
29
64
4 13
7
6
19
34
66
5
5
9
22
86
4
4
9
18
Fast 2 13
8
8
19
36
48
5
5
13
21
64
4
4
6
13
84
4
4
6
10
DC and Switching Characteristics
Table 96: Recommended Number of Simultaneously
Switching Outputs per V_CCO-GND Pair (Continued)
Package Type
Signal Standard
(IOSTANDARD)
FT256,
FG320,
VQ TQ PQ CP FG400,
100 144 208 132 FG484
LVCMOS15 Slow 2 16
10
10
19
55
48
7
7
9
31
66
5
5
9
18
Fast 2 9
9
9
13
25
47
7
7
7
16
65
5
5
5
13
LVCMOS12 Slow 2 17
11
11
16
55
Fast 2 10
10
10
10
31
PCI33_3
8
8
8
16
16
PCI66_3
8
8
8
13
13
PCIX
7
7
7
11
11
HSTL_I_18
10
10
10
16
17
HSTL_III_18
10
10
10
16
16
SSTL18_I
9
9
9
15
15
SSTL2_I
12
12
12
18
18
Differential Standards (Number of I/O Pairs or Channels)
LVDS_25
6
6
6
12
20
BLVDS_25
4
4
4
4
4
MINI_LVDS_25
6
6
6
12
20
LVPECL_25
Input Only
RSDS_25
6
6
6
12
20
DIFF_HSTL_I_18
5
5
5
8
8
DIFF_HSTL_IIII_18
5
5
5
8
8
DIFF_SSTL18_I
4
4
4
7
7
DIFF_SSTL2_I
6
6
6
9
8
Notes:
1. The numbers in this table are recommendations that assume sound
board layout practice. This table assumes the following parasitic
factors: combined PCB trace and land inductance per V_CCO and GND
pin of 1.0 nH, receiver capacitive load of 15 pF. Test limits are the
VIL/VIH voltage limits for the respective I/O standard.
2. The PQ208 results are based on physical measurements of a PQ208
package soldered to a typical printed circuit board. All other results
are based on worst-case simulation and an interpolation of the
PQ208 physical results.
3. If more than one signal standard is assigned to the I/Os of a given
bank, refer to XAPP689: Managing Ground Bounce in Large FPGAs
for information on how to perform weighted average SSO
calculations.
DS312-3 (v3.4) November 9, 2006
www.xilinx.com
137
Product Specification