XC3S100E_06 Datasheet, PDF (72/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

Functional Description
R
Master Serial Mode
In Master Serial mode (M[2:0] = <0:0:0>), the Spartan-3E
FPGA configures itself from an attached Xilinx Platform
Flash PROM, as illustrated in Figure 51. The FPGA sup-
plies the CCLK output clock from its internal oscillator to the
attached Platform Flash PROM. In response, the Platform
Flash PROM supplies bit-serial data to the FPGA’s DIN
input, and the FPGA accepts this data on each rising CCLK
edge.
+1.2V
VCCINT
P
HSWAP
VCCO_0
Serial Master
Mode
‘0’
M2
‘0’
M1
‘0’
M0
VCCO_2
DIN
CCLK
DOUT
INIT_B
Spartan-3E
V
VCCO_0
V
+2.5V
+2.5V
JTAG
TDI
TMS
TCK
TDO
TDI
TMS
TCK
VCCAUX
TDO
PROG_B
GND
DONE
+2.5V
XCFxxS = +3.3V
XCFxxP = +1.8V
VCCINT
D0
VCCO
CLK
OE/RESET
Platform Flash
XCFxx
CE
CEO
CF
TDI
TMS
TCK
VCCJ
TDO
GND
V
+2.5V
PROG_B
Recommend
open-drain
driver
Figure 51: Master Serial Mode using Platform Flash PROM
DS312-2_44_102105
All mode select pins, M[2:0], must be Low when sampled,
when the FPGA’s INIT_B output goes High. After configura-
tion, when the FPGA’s DONE output goes High, the mode
select pins are available as full-featured user-I/O pins.
P _{Similarly, the FPGA’s HSWAP pin must be Low to}
enable pull-up resistors on all user-I/O pins during configu-
ration or High to disable the pull-up resistors. The HSWAP
control must remain at a constant logic level throughout
FPGA configuration. After configuration, when the FPGA’s
DONE output goes High, the HSWAP pin is available as
full-featured user-I/O pin and is powered by the VCCO_0
supply.
The FPGA's DOUT pin is used in daisy-chain applications,
described later. In a single-FPGA application, the FPGA’s
DOUT pin is not used but is actively driving during the con-
figuration process.
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DS312-2 (v3.4) November 9, 2006
Product Specification