XC3S100E_06 Datasheet, PDF (90/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

Functional Description
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Table 59: Number of Bits to Program a Spartan-3E FPGA and Smallest Parallel Flash PROM
Spartan-3E FPGA
Uncompressed
File Sizes (bits)
Smallest Usable
Parallel Flash PROM
Minimum Required
Address Lines
XC3S100E
581,344
1 Mbit
A[16:0]
XC3S250E
1,353,728
2 Mbit
A[17:0]
XC3S500E
2,270,208
4 Mbit
A[18:0]
XC3S1200E
3,841,184
4 Mbit
A[18:0]
XC3S1600E
5,969,696
8 Mbit
A[19:0]
Compatible Flash Families
The Spartan-3E BPI configuration interface operates with a
wide variety of x8 or x8/x16 parallel NOR Flash devices.
Table 60 provides a few Flash memory families that operate
with the Spartan-3E BPI interface. Consult the data sheet
for the desired parallel NOR Flash to determine its suitabil-
ity The basic timing requirements and waveforms are pro-
vided in Byte Peripheral Interface (BPI) Configuration
Timing (Module 3).
Table 60: Compatible Parallel NOR Flash Families
Flash Vendor
Flash Memory Family
ST Microelectronics
M29W
Atmel
AT29 / AT49
Spansion (AMD, Fujitsu)
Am29 / S29
Intel
J3D StrataFlash
Macronix
MX29
CCLK Frequency
In BPI mode, the FPGA’s internal oscillator generates the
configuration clock frequency that controls all the interface
timing. The FPGA starts configuration at its lowest fre-
quency and increases its frequency for the remainder of the
configuration process if so specified in the configuration bit-
stream. The maximum frequency is specified using the
ConfigRate bitstream generator option.
Table 61: Maximum ConfigRate Settings for Parallel
Flash PROMs (Commercial Temperature Range)
Flash Read Access Time
Maximum ConfigRate
Setting
< 250 ns
3
< 115 ns
6
< 45 ns
12
Table 61 shows the maximum ConfigRate settings for vari-
ous PROM read access times over the Commercial temper-
ature operating range. See Byte Peripheral Interface (BPI)
Configuration Timing (Module 3) for more detailed infor-
mation. Despite using slower ConfigRate settings, BPI
mode is equally fast as the other configuration modes. In
BPI mode, data is accessed at the ConfigRate frequency
and internally serialized with an 8X clock frequency.
Using the BPI Interface after Configuration
After the FPGA successfully completes configuration, all
pins connected to the parallel Flash PROM are available as
user I/Os.
If not using the parallel Flash PROM after configuration,
drive LDC0 High to disable the PROM’s chip-select input.
The remainder of the BPI pins then become available to the
FPGA application, including all 24 address lines, the eight
data lines, and the LDC2, LDC1, and HDC control pins.
Because all the interface pins are user I/Os after configura-
tion, the FPGA application can continue to use the interface
pins to communicate with the parallel Flash PROM. Parallel
Flash PROMs are available in densities ranging from 1 Mbit
up to 128 Mbits and beyond. However, a single Spartan-3E
FPGA requires less than 6 Mbits for configuration. If
desired, use a larger parallel Flash PROM to contain addi-
tional non-volatile application data, such as MicroBlaze pro-
cessor code, or other user data, such as serial numbers and
Ethernet MAC IDs. In such an example, the FPGA config-
ures from parallel Flash PROM. Then using FPGA logic
after configuration, a MicroBlaze processor embedded
within the FPGA can either execute code directly from par-
allel Flash PROM or copy the code to external DDR
SDRAM and execute from DDR SDRAM. Similarly, the
FPGA application can store non-volatile application data
within the parallel Flash PROM.
The FPGA configuration data is stored starting at either at
location 0 or the top of memory (addresses all ones) or at
both locations for MultiBoot mode. Store any additional data
beginning in other available parallel Flash PROM sectors.
Do not mix configuration data and user data in the same
sector.
Similarly, the parallel Flash PROM interface can be
expanded to additional parallel peripherals.
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DS312-2 (v3.4) November 9, 2006
Product Specification