XC3S100E_06 Datasheet, PDF (16/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

Functional Description
R
Table 6: Single-Ended IOSTANDARD Bank Compatibility (Continued)
V_CCO Supply/Compatibility
Single-Ended
IOSTANDARD
HSTL_III_18
1.2V
-
1.5V
-
SSTL18_I
-
-
SSTL2_I
-
-
Notes:
1. N/R - Not required for input operation.
1.8V
Input/
Output
Input/
Output
-
2.5V
Input
Input
Input/
Output
3.3V
Input
Input
Input
Input Requirements
V_REF
Board
Termination
Voltage (V_TT)
1.1
1.8
0.9
0.9
1.25
1.25
Table 7: Differential IOSTANDARD Bank Compatibility
Differential
IOSTANDARD
LVDS_25
1.8V
Input
RSDS_25
Input
MINI_LVDS_25
Input
LVPECL_25
BLVDS_25
DIFF_HSTL_I_18
DIFF_HSTL_III_18
DIFF_SSTL18_I
DIFF_SSTL2_I
Input
Input
Input,
Output
Input,
Output
Input,
Output
Input
V_CCO Supply
2.5V
Input,
On-chip Differential Termination,
Output
Input,
On-chip Differential Termination,
Output
Input,
On-chip Differential Termination,
Output
Input
Input,
Output
Input
Input
Input
Input,
Output
3.3V
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Requirements:
V_REF
V_REF is not used
for these I/O
standards
Notes:
1. Each bank can support any two of the following: LVDS_25 outputs, MINI_LVDS_25 outputs, RSDS_25 outputs.
Differential Bank
Restriction⁽¹⁾
Applies to
Outputs Only
Applies to
Outputs Only
Applies to
Outputs Only
No Differential
Bank Restriction
(other I/O bank
restrictions might
apply)
HSTL and SSTL inputs use the Reference Voltage (V_REF) to
bias the input-switching threshold. Once a configuration
data file is loaded into the FPGA that calls for the I/Os of a
given bank to use HSTL/SSTL, a few specifically reserved
I/O pins on the same bank automatically convert to V_REF
inputs. For banks that do not contain HSTL or SSTL, V_REF
pins remain available for user I/Os or input pins.
Differential standards employ a pair of signals, one the
opposite polarity of the other. The noise canceling proper-
ties (for example, Common-Mode Rejection) of these stan-
dards permit exceptionally high data transfer rates. This
subsection introduces the differential signaling capabilities
of Spartan-3E devices.
Each device-package combination designates specific I/O
pairs specially optimized to support differential standards.
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DS312-2 (v3.4) November 9, 2006
Product Specification