XC3S100E_06 Datasheet, PDF (8/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

Introduction and Ordering Information
R
Beginning with Stepping 1 and later, the stepping level is shown in Figure 2, Figure 3, and Figure 4. Stepping 0
marked on the device using a single number character, as devices are represented with either a ‘0’ mark or no mark.
Revision History
The following table shows the revision history for this document.
Date
03/01/05
03/21/05
11/23/05
03/22/06
11/09/06
Version
1.0
1.1
2.0
3.0
3.4
Revision
Initial Xilinx release.
Added XC3S250E in CP132 package to Table 2. Corrected number of differential I/O pairs
for CP132 package. Added package markings for QFP packages (Figure 2) and
CP132/CPG132 packages (Figure 4).
Added differential HSTL and SSTL I/O standards. Updated Table 2 to indicate number of
input-only pins. Added Production Stepping information, including example top marking
diagrams.
Upgraded data sheet status to Preliminary. Added XC3S100E in CP132 package and
updated I/O counts for the XC3S1600E in FG320 package (Table 2). Added information
about dual markings for –5C and –4I product combinations to Package Marking.
Added 66 MHz PCI support and links to the Xilinx PCI LogiCORE data sheet. Indicated that
Stepping 1 parts are Production status. Promoted Module 1 to Production status.
Synchronized all modules to v3.4.
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www.xilinx.com
DS312-1 (v3.4) November 9, 2006
Product Specification