XC3S100E_06 Datasheet, PDF (152/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

R
DC and Switching Characteristics
Slave Parallel Mode Timing
PROG_B
(Input)
INIT_B
(Open-Drain)
CSI_B
(Input)
RDWR_B
(Input)
CCLK
(Input)
T_SMCCW
T_SMCSCC
T_SMDCC
T_SMCCD
T_SMCCCS
T_MCCH
T_SCCH
T_MCCL
T_SCCL
1/F_CCPAR
T_SMWCC
D0 - D7
(Inputs)
BUSY
(Output)
High-Z
Byte 0
Byte 1
T_SMCKBY
Byte n
T_SMCKBY
Byte n+1
BUSY
High-Z
DS312-3_02_103105
Notes:
1. It is possible to abort configuration by pulling CS_B Low in a given CCLK cycle, then switching RDWR_B Low or High in any subsequent
cycle for which CSI_B remains Low. The RDWR_B pin asynchronously controls the driver impedance of the D0 - D7 bus. When RDWR_B
switches High, be careful to avoid contention on the D0 - D7 bus.
Figure 76: Waveforms for Slave Parallel Configuration
Table 116: Timing for the Slave Parallel Configuration Mode
All Speed Grades
Symbol
Description
Min
Max Units
Clock-to-Output Times
T_SMCKBY
The time from the rising transition on the CCLK pin to a signal transition at the
-
BUSY pin
12.0 ns
Setup Times
T_SMDCC
The time from the setup of data at the D0-D7 pins to the active edge the CCLK 11.0
-
ns
pin
T_SMCSCC
T_SMCCW(2)
Setup time on the CSI_B pin before the active edge of the CCLK pin
Setup time on the RDWR_B pin before active edge of the CCLK pin
10.0
-
ns
23.0
-
ns
152
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DS312-3 (v3.4) November 9, 2006
Product Specification