XC3S100E_06 Datasheet, PDF (155/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

R
DC and Switching Characteristics
Table 118: Configuration Timing Requirements for Attached SPI Serial Flash
Symbol
Description
Requirement
T_CCS
SPI serial Flash PROM chip-select time
T_CCS ≤ T_MCCL1 – T_CCO
T_DSU
SPI serial Flash PROM data input setup time
T_DSU ≤ T_MCCL1 – T_CCO
T_DH
SPI serial Flash PROM data input hold time
T_DH ≤ T_MCCH1
T_V
SPI serial Flash PROM data clock-to-output time
T_V ≤ T_MCCLn – T_DCC
f_C or f_R
Maximum SPI serial Flash PROM clock frequency (also depends
on specific read command used)
Units
ns
ns
ns
ns
MHz
f_C
≥
--------------¹----------------
T_CCLKn(min)
Notes:
1. These requirements are for successful FPGA configuration in SPI mode, where the FPGA provides the CCLK frequency. The post
configuration timing can be different to support the specific needs of the application loaded into the FPGA and the resulting clock source.
2. Subtract additional printed circuit board routing delay as required by the application.
DS312-3 (v3.4) November 9, 2006
www.xilinx.com
155
Product Specification