XC3S100E_06 Datasheet, PDF (18/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

Functional Description
R
Table 8: Programmable Output Drive Current
Output Drive Current (mA)
IOSTANDARD 2
4
6
8 12 16
LVTTL
999999
LVCMOS33
999999
LVCMOS25
99999 -
LVCMOS18
9999 -
-
LVCMOS15
999 -
-
-
LVCMOS12
9-
-
-
-
-
High output current drive strength and FAST output slew
rates generally result in fastest I/O performance. However,
these same settings generally also result in transmission
line effects on the printed circuit board (PCB) for all but the
shortest board traces. Each IOB has independent slew rate
and drive strength controls. Use the slowest slew rate and
lowest output drive current that meets the performance
requirements for the end application.
Likewise, due to lead inductance, a given package supports
a limited number of simultaneous switching outputs (SSOs)
when using fast, high-drive outputs. Only use fast,
high-drive outputs when required by the application.
IOBs Organized into Banks
The Spartan-3E architecture organizes IOBs into four I/O
banks as shown in Figure 13. Each bank maintains sepa-
rate V_CCO and V_REF supplies. The separate supplies allow
each bank to independently set V_CCO. Similarly, the V_REF
supplies may be set for each bank. Refer to Table 6 and
Table 7 for V_CCO and V_REF requirements.
When working with Spartan-3E devices, most of the differ-
ential I/O standards are compatible and can be combined
within any given bank. Each bank can support any two of
the following differential standards: LVDS_25 outputs,
MINI_LVDS_25 outputs, and RSDS_25 outputs. As an
example, LVDS_25 outputs, RSDS_25 outputs, and any
other differential inputs while using on-chip differential ter-
mination are a valid combination. A combination not allowed
is a single bank with LVDS_25 outputs, RSDS_25 outputs,
and MINI_LVDS_25 outputs.
Bank 0
Bank 2
DS312-2_26_021205
Figure 13: Spartan-3E I/O Banks (top view)
I/O Banking Rules
When assigning I/Os to banks, these V_CCO rules must be
followed:
1. All V_CCO pins on the FPGA must be connected even if a
bank is unused.
2. All V_CCO lines associated within a bank must be set to
the same voltage level.
3. The V_CCO levels used by all standards assigned to the
I/Os of any given bank must agree. The Xilinx
development software checks for this. Table 6 and
Table 7 describe how different standards use the V_CCO
supply.
4. If a bank does not have any V_CCO requirements,
connect V_CCO to an available voltage, such as 2.5V or
3.3V. Some configuration modes might place additional
V_CCO requirements. Refer to Configuration for more
information.
If any of the standards assigned to the Inputs of the bank
use V_REF, then the following additional rules must be
observed:
1. All V_REF pins must be connected within a bank.
2. All V_REF lines associated with the bank must be set to
the same voltage level.
3. The V_REF levels used by all standards assigned to the
Inputs of the bank must agree. The Xilinx development
software checks for this. Table 6 describes how different
standards use the V_REF supply.
If V_REF is not required to bias the input switching thresholds,
all associated V_REF pins within the bank can be used as
user I/Os or input pins.
Package Footprint Compatibility
Sometimes, applications outgrow the logic capacity of a
specific Spartan-3E FPGA. Fortunately, the Spartan-3E
family is designed so that multiple part types are available in
pin-compatible package footprints, as described in Pinout
Descriptions in Module 4. In some cases, there are subtle
differences between devices available in the same footprint.
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DS312-2 (v3.4) November 9, 2006
Product Specification