XC3S100E_06 Datasheet, PDF (214/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

Pinout Descriptions
R
FG400: 400-ball Fine-pitch Ball Grid Array
The 400-ball fine-pitch ball grid array, FG400, supports two
different Spartan-3E FPGAs, including the XC3S1200E and
the XC3S1600E. Both devices share a common footprint for
this package as shown in Table 151 and Figure 88.
Table 151 lists all the FG400 package pins. They are sorted
by bank number and then by pin name. Pairs of pins that
form a differential I/O pair appear together in the table. The
table also shows the pin number for each pin and the pin
type, as defined earlier.
Table 151: FG400 Package Pinout (Continued)
Bank
XC3S1200E
XC3S1600E
Pin Name
FG400
Ball
Type
0
IO_L12P_0
D12
I/O
0
IO_L13N_0
E12
I/O
0
IO_L13P_0
F12
I/O
0
IO_L15N_0/GCLK5
G11
GCLK
An electronic version of this package pinout table and foot-
print diagram is available for download from the Xilinx web-
site at http://www.xilinx.com/bvdocs/publications/s3e_pin.zip.
Pinout Table
Table 151: FG400 Package Pinout
Bank
XC3S1200E
XC3S1600E
Pin Name
0
IO
0
IO
0
IO
0
IO
0
IO
0
IO
0
IO
0
IO
0
IO
0
IO
0
IO
0
IO/VREF_0
0
IO_L01N_0
0
IO_L01P_0
0
IO_L03N_0/VREF_0
0
IO_L03P_0
0
IO_L04N_0
0
IO_L04P_0
0
IO_L06N_0
0
IO_L06P_0
0
IO_L07N_0
0
IO_L07P_0
0
IO_L09N_0/VREF_0
0
IO_L09P_0
0
IO_L10N_0
0
IO_L10P_0
0
IO_L12N_0
FG400
Ball
A3
A8
A12
C7
C10
E8
E13
E16
F13
F14
G7
C11
B17
C17
A18
A19
A17
A16
A15
B15
C14
D14
A13
A14
B13
C13
C12
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VREF
I/O
I/O
VREF
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VREF
I/O
I/O
I/O
I/O
0
IO_L15P_0/GCLK4
0
IO_L16N_0/GCLK7
0
IO_L16P_0/GCLK6
0
IO_L18N_0/GCLK11
0
IO_L18P_0/GCLK10
0
IO_L19N_0
0
IO_L19P_0
0
IO_L21N_0
0
IO_L21P_0
0
IO_L22N_0/VREF_0
0
IO_L22P_0
0
IO_L24N_0/VREF_0
0
IO_L24P_0
0
IO_L25N_0
0
IO_L25P_0
0
IO_L27N_0
0
IO_L27P_0
0
IO_L28N_0
0
IO_L28P_0
0
IO_L30N_0/VREF_0
0
IO_L30P_0
0
IO_L31N_0
0
IO_L31P_0
0
IO_L32N_0/HSWAP
0
IO_L32P_0
0
IP
0
IP
0
IP_L02N_0
0
IP_L02P_0
0
IP_L05N_0
0
IP_L05P_0
0
IP_L08N_0
0
IP_L08P_0
0
IP_L11N_0
0
IP_L11P_0
F11
GCLK
E10
GCLK
E11
GCLK
A9
GCLK
A10
GCLK
F9
I/O
E9
I/O
C9
I/O
D9
I/O
B8
VREF
B9
I/O
F7
VREF
F8
I/O
A6
I/O
A7
I/O
B5
I/O
B6
I/O
D6
I/O
C6
I/O
C5
VREF
D5
I/O
A2
I/O
B2
I/O
D4
DUAL
C4
I/O
B18
INPUT
E5
INPUT
C16 INPUT
D16 INPUT
D15 INPUT
C15 INPUT
E14
INPUT
E15
INPUT
G14 INPUT
G13 INPUT
214
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DS312-4 (v3.4) November 9, 2006
Product Specification