XC3S100E_06 Datasheet, PDF (38/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

Functional Description
Block RAM Port Signal Definitions
Caution! Representations of the dual-port primitive
RAMB16_S[w_A]_S[w_B] and the single-port primitive
RAMB16_S[w] with their associated signals are shown in
Figure 32a and Figure 32b, respectively. These signals are
defined in Table 23. The control signals (WE, EN, CLK, and
SSR) on the block RAM are active High. However, optional
R
inverters on the control signals change the polarity of the
active edge to active Low.
DESIGN NOTE:
! ^{Whenever a block RAM port is enabled (ENA or ENB}
= High), all address transitions must meet the data
sheet setup and hold times with respect to the port
clock (CLKA or CLKB), as shown in Table 102,
page 142.This requirement must be met even if the
RAM read output is of no interest.
WEA
ENA
SSRA
CLKA
ADDRA[r_A–1:0]
DIA[w_A–p_A–1:0]
DIPA[p_A–1:0]
RAMB16_S_WA_S_WB
DOPA[p_A–1:0]
DOA[w_A–p_A–1:0]
WEB
ENB
SSRB
CLKB
ADDRB[r_B–1:0]
DIB[w_B–p_B–1:0]
DIPB[p_B–1:0]
DOPB[p_B–1:0]
DOB[w_B–p_B–1:0]
WE
EN
SSR
CLK
ADDR[r–1:0]
DI[w–p–1:0]
DIP[p–1:0]
RAMB16_Sw
DOP[p–1:0]
DO[w–p–1:0]
(a) Dual-Port
(b) Single-Port
DS312-2_03_111105
Notes:
1. w_A and w_B are integers representing the total data path width (i.e., data bits plus parity bits) at Ports A and B, respectively.
2. p_A and p_B are integers that indicate the number of data path lines serving as parity bits.
3. r_A and r_B are integers representing the address bus width at ports A and B, respectively.
4. The control signals CLK, WE, EN, and SSR on both ports have the option of inverted polarity.
Figure 32: Block RAM Primitives
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DS312-2 (v3.4) November 9, 2006
Product Specification