XC3S100E_06 Datasheet, PDF (10/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

Functional Description
R
T
TFF1
T1
D
Q
CE
CK
SR REV
DDR
MUX
TCE
T2
D
Q
TFF2
CE
CK
SR REV
Three-state Path
O1
OTCLK1
OCE
O2
OTCLK2
D
CE
CK
SR
OFF1
Q
REV
DDR
MUX
D
CE
CK
SR
Q
OFF2
REV
Program-
mable
Output
Driver
Output Path
VCCO
Pull-Up
Pull-
Down
ESD
I/O
Pin
ESD
Keeper
Latch
I
Programmable
Delay
LVCMOS, LVTTL, PCI
IQ1
IDDRIN1
IDDRIN2
ICLK1
ICE
IQ2
Programmable
Delay
D
Q
CE
IFF1
CK
SR REV
D
Q
IFF2
CE
Single-ended Standards
using VREF
Differential Standards
V_REF
Pin
I/O Pin
from
Adjacent
IOB
ICLK2
SR
CK
SR REV
REV
Notes:
Input Path
DS312-2_19_110606
1. All IOB control and output path signals have an inverting polarity option wihtin the IOB.
2. IDDRIN1/IDDRIN2 signals shown with dashed lines connect to the adjacent IOB in a differential pair only, not to the FPGA fabric.
Figure 5: Simplified IOB Diagram
10
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DS312-2 (v3.4) November 9, 2006
Product Specification