XC3S100E_06 Datasheet, PDF (39/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

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Functional Description
Table 23: Block RAM Port Signals
Signal
Description
Port A
Signal
Name
Port B
Signal
Name
Address Bus
ADDRA ADDRB
Data Input Bus
DIA
DIB
Parity Data
Input(s)
DIPA
DIPB
Data Output Bus
DOA
DOB
Parity Data
Output(s)
Write Enable
DOPA
DOPB
WEA
WEB
Clock Enable
Set/Reset
Clock
ENA
ENB
SSRA
CLKA
SSRB
CLKB
Direction
Input
Input
Input
Output
Output
Input
Input
Input
Input
Function
The Address Bus selects a memory location for read or write operations.
The width (w) of the port’s associated data path determines the number of
available address lines (r), as per Table 22.
Whenever a port is enabled (ENA or ENB = High), address transitions
must meet the data sheet setup and hold times with respect to the port
clock (CLKA or CLKB), as shown in Table 102, page 142.This requirement
must be met even if the RAM read output is of no interest.
Data at the DI input bus is written to the RAM location specified by the
address input bus (ADDR) during the active edge of the CLK input, when
the clock enable (EN) and write enable (WE) inputs are active.
It is possible to configure a port’s DI input bus width (w-p) based on
Table 22. This selection applies to both the DI and DO paths of a given
port.
Parity inputs represent additional bits included in the data input path.
Although referred to herein as “parity” bits, the parity inputs and outputs
have no special functionality for generating or checking parity and can be
used as additional data bits. The number of parity bits ‘p’ included in the
DI (same as for the DO bus) depends on a port’s total data path width (w).
See Table 22.
Data is written to the DO output bus from the RAM location specified by
the address input bus, ADDR. See the DI signal description for DO port
width configurations.
Basic data access occurs on the active edge of the CLK when WE is
inactive and EN is active. The DO outputs mirror the data stored in the
address ADDR memory location. Data access with WE active if the
WRITE_MODE attribute is set to the value: WRITE_FIRST, which
accesses data after the write takes place. READ_FIRST accesses data
before the write occurs. A third attribute, NO_CHANGE, latches the DO
outputs upon the assertion of WE. See Block RAM Data Operations for
details on the WRITE_MODE attribute.
Parity outputs represent additional bits included in the data input path. The
number of parity bits ‘p’ included in the DI bus (same as for the DO bus)
depends on a port’s total data path width (w). See the DIP signal
description for configuration details.
When asserted together with EN, this input enables the writing of data to
the RAM. When WE is inactive with EN asserted, read operations are still
possible. In this case, a latch passes data from the addressed memory
location to the DO outputs.
When asserted, this input enables the CLK signal to perform read and
write operations to the block RAM. When inactive, the block RAM does not
perform any read or write operations.
When asserted, this pin forces the DO output latch to the value of the
SRVAL attribute. It is synchronized to the CLK signal.
This input accepts the clock signal to which read and write operations are
synchronized. All associated port inputs are required to meet setup times
with respect to the clock signal’s active edge. The data output bus
responds after a clock-to-out delay referenced to the clock signal’s active
edge.
DS312-2 (v3.4) November 9, 2006
www.xilinx.com
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Product Specification