XC3S100E_06 Datasheet, PDF (69/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

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Functional Description
Table 45: Pin Behavior during Configuration (Continued)
Pin Name
D3
D2
D1
D0/DIN
RDWR_B
A23
A22
A21
A20
A19/VS2
A18/VS1
A17/VS0
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
LDC0
LDC1
LDC2
HDC
SPI (Serial
Master Serial
Flash)
DIN
DIN
VS2
VS1
VS0
BPI (Parallel
NOR Flash)
D3
D2
D1
D0
RDWR_B
A23
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
LDC0
LDC1
LDC2
HDC
JTAG
Slave
Parallel
D3
D2
D1
D0
RDWR_B
Slave Serial
DIN
Supply/
I/O Bank
2
2
2
2
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Notes:
1. Gray shaded cells represent pins that are in a high-impedance state (Hi-Z, floating) during configuration. These pins have an optional
internal pull-up resistor to their respective V_CCO supply pin that is active throughout configuration if the HSWAP input is Low.
2. Yellow shaded cells represent pins with an internal pull-up resistor to its respective voltage supply rail that is active during
configuration, regardless of the HSWAP pin.
The HSWAP pin itself has an pull-up resistor enabled during
configuration. However, the VCCO_0 supply voltage must
be applied before the pull-up resistor becomes active. If the
VCCO_0 supply ramps after the VCCO_2 power supply, do
not let HSWAP float; tie HSWAP to the desired logic level
externally.
Spartan-3E FPGAs have only six dedicated configuration
pins, including the DONE and PROG_B pins, and the four
JTAG boundary-scan pins: TDI, TDO, TMS, and TCK. All
other configuration pins are dual-purpose I/O pins and are
available to the FPGA application after the DONE pin goes
High. See Start-Up for additional information.
DS312-2 (v3.4) November 9, 2006
www.xilinx.com
69
Product Specification