XC3S100E_06 Datasheet, PDF (125/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

R
Internal
Logic
DC and Switching Characteristics
V_OUTP
P
N
V_OUTN
Differential
I/O Pair Pins
V_OUTN
V_OUTP
GND level
50%
V_OCM
V_OD
V_OH
V_OL
V_OCM = Output common mode voltage =
V_OUTP + V_OUTN
2
V_OD = Output differential voltage = ^V_OUTP ^{- V}_OUTN
V_OH = Output voltage indicating a High logic level
V_OL ^{= Output voltage indicating a Low logic level} DS312-3_03_021505
Figure 71: Differential Output Voltages
Table 82: DC Characteristics of User I/Os Using Differential Signal Standards
V_OD
ΔV_OD
V_OCM
ΔV_OCM
V_OH
IOSTANDARD
Min Typ Max Min Max Min Typ Max Min Max
Min
Attribute
(mV) (mV) (mV) (mV) (mV) (V)
(V)
(V) (mV) (mV)
(V)
V_OL
Max
(V)
LVDS_25
250 350 450
–
– 1.125 – 1.375 –
–
–
–
BLVDS_25
250 350 450
–
–
–
1.20
–
–
–
–
–
MINI_LVDS_25
300
–
600
–
50 1.0
–
1.4
–
50
–
–
RSDS_25
100
–
400
–
–
1.1
–
1.4
–
–
–
–
DIFF_HSTL_I_18
–
–
–
–
–
–
–
–
–
– V_CCO – 0.4
0.4
DIFF_HSTL_III_18
–
–
–
–
–
–
–
–
–
– V_CCO – 0.4
0.4
DIFF_SSTL18_I
–
–
–
–
–
–
–
–
–
–
V_TT + 0.475 V_TT – 0.475
DIFF_SSTL2_I
–
–
–
–
–
–
–
–
–
– V_TT + 0.61 V_TT – 0.61
Notes:
1. The numbers in this table are based on the conditions set forth in Table 76 and Table 81.
2. Output voltage measurements for all differential standards are made with a termination resistor (R_T) of 100Ω across the N and P pins of the
differential signal pair. The exception is for BLVDS, shown in Figure 72 below.
3. At any given time, no more than two of the following differential output standards may be assigned to an I/O bank: LVDS_25, RSDS_25,
MINI_LVDS_25
VCCO = 2.5V
1/4th of Bourns
Part Number
CAT16-LV4F12
165Ω
Z0 = 50Ω
1/4th of Bourns
Part Number
CAT16-PT4F4
VCCO = 2.5V
140Ω _{Z0 = 50Ω}
100Ω
165Ω
ds312-3_07_102105
Figure 72: External Termination Resistors for BLVDS I/Os
DS312-3 (v3.4) November 9, 2006
www.xilinx.com
125
Product Specification