XC3S100E_06 Datasheet, PDF (131/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

R
DC and Switching Characteristics
Table 91: Timing for the IOB Output Path
Symbol
Description
Conditions
Clock-to-Output Times
T_IOCKP
When reading from the
Output Flip-Flop (OFF), the
time from the active transition
at the OCLK input to data
appearing at the Output pin
LVCMOS25⁽²⁾, 12 mA
output drive, Fast slew
rate
Propagation Times
T_IOOP
The time it takes for data to
travel from the IOB’s O input
to the Output pin
LVCMOS25⁽²⁾, 12 mA
output drive, Fast slew
rate
T_IOOLP
The time it takes for data to
travel from the O input
through the OFF latch to the
Output pin
Set/Reset Times
T_IOSRP
Time from asserting the
OFF’s SR input to
setting/resetting data at the
Output pin
LVCMOS25⁽²⁾, 12 mA
output drive, Fast slew
rate
T_IOGSRQ
Time from asserting the
Global Set Reset (GSR)
input on the
STARTUP_SPARTAN3E
primitive to setting/resetting
data at the Output pin
Device
Speed Grade
-0
-5
-4
Abs. Min. Max Max
All
0.88 2.18 2.50
All
0.90 2.24 2.58
0.94 2.32 2.67
All
1.32 3.27 3.76
3.38 8.40 9.65
Units
ns
ns
ns
ns
ns
Notes:
1. The numbers in this table are tested using the methodology presented in Table 94 and are based on the operating conditions set forth in
Table 76 and Table 79.
2. This time requires adjustment whenever a signal standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the data
Output. When this is true, add the appropriate Output adjustment from Table 93.
DS312-3 (v3.4) November 9, 2006
www.xilinx.com
131
Product Specification