XC3S100E_06 Datasheet, PDF (93/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

R
Functional Description
+1.2V
V
VCCINT
P
HSWAP
VCCO_0
VCCO_0
I
VCCO_1
V
LDC0
LDC1
HDC
Not available
in VQ100
package
LDC2
A[16:0]
VCC
CE# x8 or
OE# ^x8/x16
WE#
Flash
PROM
BYTE#
D
DQ[15:7]
BPI Mode
‘0’
M2
‘1’
M1
A
M0
VCCO_2
V
D[7:0]
A[23:17]
DQ[7:0]
A[n:0]
GND
2.5V
JTAG
TDI
TMS
TCK
TDO
Spartan-3E _BUSY
FPGA _CCLK
‘0’
CSI_B
CSO_B
‘0’
RDWR_B
INIT_B
TDI
TMS
TCK
VCCAUX
TDO
+2.5V
PROG_B
DONE
+2.5V
V
GND
+1.2V
VCCINT
P
HSWAP
VCCO_0
VCCO_0
VCCO_1
VCCO_1
CCLK
D[7:0]
Slave
Parallel
Mode
‘1’
‘1’
‘0’
‘0’
VCCO_2
M2
D[7:0]
M1
M0
Spartan-3E _BUSY
CCLK ^FPGA
CSI_B
CSO_B
RDWR_B
INIT_B
TDI
TMS
TCK
VCCAUX
TDO
PROG_B
GND
DONE
V
+2.5V
CSO_B
PROG_B
Recommend
open-drain
driver
PROG_B
TCK
TMS
DONE
INIT_B
Figure 59: Daisy-Chaining from BPI Flash Mode
DS312-2_50_103105
In-System Programming Support
I _{In a production application, the parallel Flash PROM is}
usually preprogrammed before it is mounted on the printed
circuit board. In-system programming support is available
from third-party boundary-scan tool vendors and from some
third-party PROM programmers using a socket adapter with
attached wires. To gain access to the parallel Flash signals,
drive the FPGA’s PROG_B input Low with an open-drain
driver. This action places all FPGA I/O pins, including those
attached to the parallel Flash, in high-impedance (Hi-Z). If
the HSWAP input is Low, the I/Os have pull-up resistors to
the V_CCO input on their respective I/O bank. The external
programming hardware then has direct access to the paral-
lel Flash pins. The programming access points are high-
lighted in the gray boxes in Figure 58 and Figure 59.
The FPGA itself can also be used as a parallel Flash PROM
programmer during development and test phases. Initially,
an FPGA-based programmer is downloaded into the FPGA
via JTAG. Then the FPGA performs the Flash PROM pro-
gramming algorithms and receives programming data from
the host via the FPGA’s JTAG interface. See Chapter 11 in
Embedded System Tools Reference Manual.
Dynamically Loading Multiple Configuration
Images Using MultiBoot Option
After the FPGA configures itself using BPI mode from one
end of the parallel Flash PROM, then the FPGA can trigger
a MultiBoot event and reconfigure itself from the opposite
end of the parallel Flash PROM. MultiBoot is only available
when using BPI mode and only for applications with a single
Spartan-3E FPGA.
By default, MultiBoot mode is disabled. To trigger a Multi-
Boot event, assert a Low pulse lasting at least 300 ns on the
MultiBoot Trigger (MBT) input to the
STARTUP_SPARTAN3E library primitive. When the MBT
signal returns High after the 300 ns or longer pulse, the
FPGA automatically reconfigures from the opposite end of
the parallel Flash memory.
Figure 60 shows an example usage. At power up, the FPGA
loads itself from the attached parallel Flash PROM. In this
example, the M0 mode pin is Low so the FPGA starts at
address 0 and increments through the Flash PROM mem-
ory locations. After the FPGA completes configuration, the
application initially loaded into the FPGA performs a
board-level or system test using FPGA logic. If the test is
DS312-2 (v3.4) November 9, 2006
www.xilinx.com
93
Product Specification