XC3S100E_06 Datasheet, PDF (130/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

R
DC and Switching Characteristics
Table 89: Propagation Times for the IOB Input Path
Symbol
Description
Conditions
Propagation Times
T_IOPLI
The time it takes for data to
travel from the Input pin
through the IFF latch to the
I output with no input delay
programmed
LVCMOS25⁽²⁾,
IFD_DELAY_VALUE = 0
T_IOPLID
The time it takes for data to
travel from the Input pin
through the IFF latch to the
I output with the input delay
programmed
LVCMOS25⁽²⁾,
IFD_DELAY_VALUE =
default software setting
IFD_
DELAY_
VALUE=
Device
0
All
2 XC3S100E
3
All Others
Speed Grade
-5
-4
Max
Max
1.96
2.25
5.40
5.97
6.30
7.20
Units
ns
ns
Notes:
1. The numbers in this table are tested using the methodology presented in Table 94 and are based on the operating conditions set forth in
Table 76 and Table 79.
2. This propagation time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. When this is
true, add the appropriate Input adjustment from Table 90.
Table 90: Input Timing Adjustments by IOSTANDARD
Convert Input Time from
LVCMOS25 to the
Following Signal Standard
(IOSTANDARD)
Add the
Adjustment Below
Speed Grade
-5
-4
Units
Single-Ended Standards
LVTTL
0.42
0.43
ns
LVCMOS33
0.42
0.43
ns
LVCMOS25
0
0
ns
LVCMOS18
0.96
0.98
ns
LVCMOS15
0.62
0.63
ns
LVCMOS12
0.26
0.27
ns
PCI33_3
0.41
0.42
ns
PCI66_3
0.41
0.42
ns
PCIX
0.22
0.22
ns
HSTL_I_18
0.12
0.12
ns
HSTL_III_18
0.17
0.17
ns
SSTL18_I
0.30
0.30
ns
SSTL2_I
0.15
0.15
ns
Table 90: Input Timing Adjustments by IOSTANDARD
Convert Input Time from
LVCMOS25 to the
Following Signal Standard
(IOSTANDARD)
Add the
Adjustment Below
Speed Grade
-5
-4
Units
Differential Standards
LVDS_25
0.48
0.49
ns
BLVDS_25
0.39
0.39
ns
MINI_LVDS_25
0.48
0.49
ns
LVPECL_25
0.27
0.27
ns
RSDS_25
0.48
0.49
ns
DIFF_HSTL_I_18
0.48
0.49
ns
DIFF_HSTL_III_18
0.48
0.49
ns
DIFF_SSTL18_I
0.30
0.30
ns
DIFF_SSTL2_I
0.32
0.32
ns
Notes:
1. The numbers in this table are tested using the methodology
presented in Table 94 and are based on the operating conditions
set forth in Table 76, Table 79, and Table 81.
2. These adjustments are used to convert input path times originally
specified for the LVCMOS25 standard to times that correspond to
other signal standards.
130
www.xilinx.com
DS312-3 (v3.4) November 9, 2006
Product Specification