XC3S100E_06 Datasheet, PDF (153/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

R
DC and Switching Characteristics
Table 116: Timing for the Slave Parallel Configuration Mode (Continued)
All Speed Grades
Symbol
Description
Min
Max Units
Hold Times
T_SMCCD
The time from the active edge of the CCLK pin to the point when data is last 1.0
held at the D0-D7 pins
-
ns
T_SMCCCS
The time from the active edge of the CCLK pin to the point when a logic level
0
is last held at the CSO_B pin
-
ns
T_SMWCC
The time from the active edge of the CCLK pin to the point when a logic level
0
is last held at the RDWR_B pin
-
ns
Clock Timing
T_CCH
T_CCL
F_CCPAR
The High pulse width at the CCLK input pin
The Low pulse width at the CCLK input pin
Frequency of the clock
signal at the CCLK input
pin
No bitstream
compression
Not using the BUSY pin⁽²⁾
Using the BUSY pin
With bitstream compression
5
-
ns
5
-
ns
0
50 MHz
0
66 MHz
0
20 MHz
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 76.
2. In the Slave Parallel mode, it is necessary to use the BUSY pin when the CCLK frequency exceeds this maximum specification.
3. Some Xilinx documents refer to Parallel modes as “SelectMAP” modes.
DS312-3 (v3.4) November 9, 2006
www.xilinx.com
153
Product Specification