XC3S100E_06 Datasheet, PDF (175/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

R
Pinout Descriptions
User I/Os by Bank
Table 133 shows how the 83 available user-I/O pins are dis-
tributed on the XC3S100E FPGA packaged in the CP132
package. Table 134 indicates how the 92 available user-I/O
pins are distributed on the XC3S250E and the XC3S500E
FPGAs in the CP132 package.
Table 133: User I/Os Per Bank for the XC3S100E in the CP132 Package
Package
Maximum
Edge
I/O Bank
I/O
I/O
All Possible I/O Pins by Type
INPUT
DUAL
VREF
CLK
Top
0
18
6
2
1
1
8
Right
1
23
0
0
21
2
0⁽¹⁾
Bottom
2
22
0
0
20
2
0⁽¹⁾
Left
3
20
10
0
0
2
8
TOTAL
83
16
2
42
7
16
Notes:
1. The eight global clock pins in this bank have optional functionality during configuration and are counted in the DUAL column.
Table 134: User I/Os Per Bank for the XC3S250E and XC3S500E in the CP132 Package
Package
Maximum
Edge
I/O Bank
I/O
I/O
All Possible I/O Pins by Type
INPUT
DUAL
VREF
Top
0
22
11
0
1
2
Right
1
23
0
0
21
2
Bottom
2
26
0
0
24
2
Left
3
21
11
0
0
2
TOTAL
92
22
0
46
8
CLK
8
0⁽¹⁾
0⁽¹⁾
8
16
Notes:
1. The eight global clock pins in this bank have optional functionality during configuration and are counted in the DUAL column.
DS312-4 (v3.4) November 9, 2006
www.xilinx.com
175
Product Specification