XC3S100E_06 Datasheet, PDF (6/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

Introduction and Ordering Information
R
Package Marking
Figure 2 provides a top marking example for Spartan-3E
FPGAs in the quad-flat packages. Figure 3 shows the top
marking for Spartan-3E FPGAs in BGA packages except
the 132-ball chip-scale package (CP132 and CPG132). The
markings for the BGA packages are nearly identical to those
for the quad-flat packages, except that the marking is
rotated with respect to the ball A1 indicator. Figure 4 shows
the top marking for Spartan-3E FPGAs in the CP132 and
CPG132 packages.
Use the seven digits of the Lot Code to access additional
information for a specific device using the Xilinx web-based
Genealogy Viewer.
On the QFP and BGA packages, the optional numerical
Stepping Code follows the Lot Code. If no Stepping Code
appears, then the device is Stepping 0.
The “5C” and “4I” part combinations may be dual marked
as “5C/4I”. All “5C” and “4I” part combinations use the
Stepping 1 production silicon and have a ‘1’ Stepping Code
mark.
Mask Revision Code
Device Type
Package
Speed Grade
Temperature Range
R
SPARTAN ^R
XC3S250E^TM
PQ208AGQ0525
D1234567A
4C
Fabrication Code
Process Technology
Date Code
Stepping Code (optional)
Lot Code
Pin P1
DS312-1_06_102905
Figure 2: Spartan-3E QFP Package Marking Example
BGA Ball A1
Device Type
Package
Speed Grade
Temperature Range
R
SPARTAN ^R
XC3S250E^TM
FT256AGQ0525
D1234567A
4C
Mask Revision Code
Fabrication Code
Process Code
Date Code
Stepping Code (optional)
Lot Code
DS312-1_02_090105
Figure 3: Spartan-3E BGA Package Marking Example
Ball A1
3S250E
Device Type
Lot Code
F1234567-0525
Date Code
PHILIPPINES
Temperature Range
Package
C5 = CP132
C5AGQ 4C
C6 = CPG132
Speed Grade
Process Code
Mask Revision Code
Fabrication Code
DS312-1_05_032105
Figure 4: Spartan-3E CP132 and CPG132 Package Marking Example
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www.xilinx.com
DS312-1 (v3.4) November 9, 2006
Product Specification