XC3S100E_06 Datasheet, PDF (116/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

Functional Description
R
Date
10/02/06
11/09/06
Version
3.3
3.4
Revision
Clarified that the block RAM Readback feature is available either on the -5 speed grade or the
Industrial temperature range.
Updated the description of the Input Delay Functions. The ODDR2 flip-flop with C0 or C1
Alignment is no longer supported. Updated Figure 5. Updated Table 6 for improved PCI
input voltage tolerance. Replaced missing text in Clock Buffers/Multiplexers. Updated SPI
Flash devices in Table 52. Updated parallel NOR Flash devices in Table 60. Direct, SPI
Flash in-system Programming Support was added beginning with ISE 8.1i iMPACT
software for STMicro and Atmel SPI PROMs. Updated Table 70 and Table 71 as Stepping
1 is in full production. Freshened various hyperlinks. Promoted Module 2 to Production
status.
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DS312-2 (v3.4) November 9, 2006
Product Specification