XC3S100E_06 Datasheet, PDF (138/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

DC and Switching Characteristics
Configurable Logic Block (CLB) Timing
Table 97: CLB (SLICEM) Timing
Symbol
Description
Clock-to-Output Times
T_CKO
When reading from the FFX (FFY) Flip-Flop,
the time from the active transition at the CLK
input to data appearing at the XQ (YQ) output
Setup Times
T_AS
Time from the setup of data at the F or G input
to the active transition at the CLK input of the
CLB
T_DICK
Time from the setup of data at the BX or BY
input to the active transition at the CLK input of
the CLB
Hold Times
T_AH
Time from the active transition at the CLK input
to the point where data is last held at the F or
G input
T_CKDI
Time from the active transition at the CLK input
to the point where data is last held at the BX or
BY input
Clock Timing
T_CH
The High pulse width of the CLB’s CLK signal
T_CL
The Low pulse width of the CLK signal
F_TOG
Toggle frequency (for export control)
Propagation Times
T_ILO
The time it takes for data to travel from the
CLB’s F (G) input to the X (Y) output
Set/Reset Pulse Width
T_{RPW_CLB}
The minimum allowable pulse width, High or
Low, to the CLB’s SR input
Speed Grade
-5
-4
Min
Max
Min
Max
-
0.52
-
0.60
0.46
-
0.52
-
0.32
-
0.36
-
0
-
0
-
0
-
0
-
0.70
-
0.80
-
0.70
-
0.80
-
0
657
0
572
-
0.66
-
0.76
1.00
-
1.15
-
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 76.
R
Units
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns
138
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DS312-3 (v3.4) November 9, 2006
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