XC3S100E_06 Datasheet, PDF (86/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

Functional Description
R
+1.2V
VCCINT
P
HSWAP
VCCO_0
VCCO_0
I
VCCO_1
V
LDC0
LDC1
HDC
Not available
in VQ100
package
LDC2
A[16:0]
+2.5V
JTAG
TDI
TMS
TCK
TDO
BPI Mode
‘0’
M2
‘1’
M1
A
M0
VCCO_2
D[7:0]
A[23:17]
Spartan-3E _BUSY
FPGA
CCLK
‘0’
CSI_B
CSO_B
‘0’
RDWR_B
INIT_B
TDI
TMS
TCK
VCCAUX
TDO
PROG_B
GND
DONE
V
V
+2.5V
V
VCCO
CE#
OE#
WE#
x8 or
x8/x16
Flash
PROM
BYTE#
D
DQ[15:7]
DQ[7:0]
A[n:0]
GND
+2.5V
PROG_B
Recommend
open-drain
driver
DS312-2_49_103105
Figure 58: Byte-wide Peripheral Interface (BPI) Mode Configured from Parallel NOR Flash PROMs
A _{During configuration, the value of the M0 mode pin}
determines how the FPGA generates addresses, as shown
Table 57. When M0 = 0, the FPGA generates addresses
starting at 0 and increments the address on every falling
CCLK edge. Conversely, when M0 = 1, the FPGA gener-
ates addresses starting at 0xFF_FFFF (all ones) and decre-
ments the address on every falling CCLK edge.
Table 57: BPI Addressing Control
M2 M1 M0 Start Address Addressing
0
0
Incrementing
01
1 0xFF_FFFF Decrementing
86
www.xilinx.com
DS312-2 (v3.4) November 9, 2006
Product Specification