XC3S100E_06 Datasheet, PDF (32/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

Functional Description
R
STARTUP_SPARTAN3E primitive. See Global Controls
(STARTUP_SPARTAN3E).
Table 17: Slice Storage Element Initialization
Signal
Description
SR
Set/Reset input. Forces the storage element
into the state specified by the attribute SRHIGH
or SRLOW. SRHIGH forces a logic “1” when SR
is asserted. SRLOW forces a logic “0”. For each
slice, set and reset can be set to be
synchronous or asynchronous.
REV
Reverse of Set/Reset input. A second input
(BY) forces the storage element into the
opposite state. The reset condition is
predominant over the set condition if both are
active. Same synchronous/asynchronous
setting as for SR.
GSR
Global Set/Reset. GSR defaults to active High
but can be inverted by adding an inverter in
front of the GSR input of the
STARTUP_SPARTAN3E element. The initial
state after configuration or GSR is defined by a
separate INIT0 and INIT1 attribute. By default,
setting the SRLOW attribute sets INIT0, and
setting the SRHIGH attribute sets INIT1.
Distributed RAM
The LUTs in the SLICEM can be programmed as distributed
RAM. This type of memory affords moderate amounts of
data buffering anywhere along a data path. One SLICEM
LUT stores 16 bits (RAM16). The four LUT inputs F[4:1] or
G[4:1] become the address lines labeled A[4:1] in the
device model and A[3:0] in the design components, provid-
ing a 16x1 configuration in one LUT. Multiple SLICEM LUTs
can be combined in various ways to store larger amounts of
data, including 16x4, 32x2, or 64x1 configurations in one
CLB. The fifth and sixth address lines required for the
32-deep and 64-deep configurations, respectively, are
implemented using the BX and BY inputs, which connect to
the write enable logic for writing and the F5MUX and
F6MUX for reading.
Writing to distributed RAM is always synchronous to the
SLICEM clock (WCLK for distributed RAM) and enabled by
the SLICEM SR input which functions as the active-High
Write Enable (WE). The read operation is asynchronous,
and, therefore, during a write, the output initially reflects the
old data at the address being written.
The distributed RAM outputs can be captured using the
flip-flops within the SLICEM element. The WE write-enable
control for the RAM and the CE clock-enable control for the
flip-flop are independent, but the WCLK and CLK clock
inputs are shared. Because the RAM read operation is
asynchronous, the output data always reflects the currently
addressed RAM location.
A dual-port option combines two LUTs so that memory
access is possible from two independent data lines. The
same data is written to both 16x1 memories but they have
independent read address lines and outputs. The dual-port
function is implemented by cascading the G-LUT address
lines, which are used for both read and write, to the F-LUT
write address lines (WF[4:1] in Figure 15), and by cascad-
ing the G-LUT data input D1 through the DIF_MUX in
Figure 15 and to the D1 input on the F-LUT. One CLB pro-
vides a 16x1 dual-port memory as shown in Figure 26.
Any write operation on the D input and any read operation
on the SPO output can occur simultaneously with and inde-
pendently from a read operation on the second read-only
port, DPO.
D
A[3:0]
WE
WCLK
SLICEM
16x1
LUT
RAM
(Read/
Write)
Optional
Register
SPO
DPRA[3:0]
16x1
LUT
RAM
(Read
Only)
DPO
Optional
Register
DS312-2_41_021305
Figure 26: RAM16X1D Dual-Port Usage
32
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DS312-2 (v3.4) November 9, 2006
Product Specification