XC3S100E_06 Datasheet, PDF (106/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

Functional Description
R
Power-On
Set PROG_B Low
after Power-On
Load
JPROG
instruction
V_CCINT >1V
and V_CCAUX > 2V
No
and V_CCO Bank 2 > 1V
Yes
Clear
configuration
memory
No
INIT_B = High?
Yes
PROG_B = Low
No
Yes
Sample
mode pins
(JTAG port becomes
available)
Load CFG_IN
instruction
Load configuration
data frames
CRC
correct?
No _{INIT_B goes Low.}
Abort Start-Up
Yes
Synchronous
TAP reset
(Clock five 1's
on TMS)
Load JSTART
instruction
Start-Up
sequence
User mode
Yes
No
Reconfigure?
DS312-2_59_051706
Figure 68: Boundary-Scan Configuration Flow Diagram
106
www.xilinx.com
DS312-2 (v3.4) November 9, 2006
Product Specification