XC3S100E_06 Datasheet, PDF (134/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

R
DC and Switching Characteristics
Timing Measurement Methodology
When measuring timing parameters at the programmable
I/Os, different signal standards call for different test condi-
tions. Table 94 lists the conditions to use for each standard.
The method for measuring Input timing is as follows: A sig-
nal that swings between a Low logic level of V_L and a High
logic level of V_H is applied to the Input under test. Some
standards also require the application of a bias voltage to
the V_REF pins of a given bank to properly set the
input-switching threshold. The measurement point of the
Input signal (V_M) is commonly located halfway between V_L
and V_H.
The Output test setup is shown in Figure 73. A termination
voltage V_T is applied to the termination resistor R_T, the other
end of which is connected to the Output. For each standard,
R_T and V_T generally take on the standard values recom-
mended for minimizing signal reflections. If the standard
does not ordinarily use terminations (e.g., LVCMOS,
LVTTL), then R_T is set to 1MΩ to indicate an open connec-
tion, and V_T is set to zero. The same measurement point
(V_M) that was used at the Input is also used at the Output.
V_T (V_REF)
FPGA Output
R_T (R_REF)
V_M (V_MEAS)
C_L (C_REF)
ds312-3_04_090105
Notes:
1. The names shown in parentheses are
used in the IBIS file.
Figure 73: Output Test Setup
Table 94: Test Methods for Timing Measurement at I/Os
Signal Standard
(IOSTANDARD)
Single-Ended
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
PCI33_3
Rising
Falling
PCI66_3
Rising
Falling
PCIX
Rising
Falling
HSTL_I_18
HSTL_III_18
SSTL18_I
SSTL2_I
Differential
LVDS_25
BLVDS_25
MINI_LVDS_25
LVPECL_25
RSDS_25
V_REF (V)
-
-
-
-
-
-
-
Inputs
V_L (V)
0
0
0
0
0
0
Note 3
V_H (V)
3.3
3.3
2.5
1.8
1.5
1.2
Note 3
-
Note 3
Note 3
-
Note 3
Note 3
0.9
1.1
0.9
1.25
-
-
-
-
-
V_REF – 0.5
V_REF – 0.5
V_REF – 0.5
V_REF – 0.75
V_REF + 0.5
V_REF + 0.5
V_REF + 0.5
V_REF + 0.75
V_ICM – 0.125
V_ICM – 0.125
V_ICM – 0.125
V_ICM – 0.3
V_ICM – 0.1
V_ICM + 0.125
V_ICM + 0.125
V_ICM + 0.125
V_ICM + 0.3
V_ICM + 0.1
Outputs
R_T (Ω)
V_T (V)
1M
0
1M
0
1M
0
1M
0
1M
0
1M
0
25
0
25
3.3
25
0
25
3.3
25
0
25
3.3
50
0.9
50
1.8
50
0.9
50
1.25
50
1.2
1M
0
50
1.2
1M
0
50
1.2
Inputs and
Outputs
V_M (V)
1.4
1.65
1.25
0.9
0.75
0.6
0.94
2.03
0.94
2.03
0.94
2.03
V_REF
V_REF
V_REF
V_REF
V_ICM
V_ICM
V_ICM
V_ICM
V_ICM
134
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DS312-3 (v3.4) November 9, 2006
Product Specification