XC3S100E_06 Datasheet, PDF (52/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

Functional Description
R
Table 31: Direct Clock Input and Optional External Feedback to Left-Edge DCMs (XC3S1200E and XC3S1600E)
Diff.
Single-Ended Pin Number by Package Type
Clock _{VQ100 CP132 TQ144 PQ208 FT256 FG320 FG400 FG484}
Left Edge
LHCLK DCM/BUFGMUX
BUFGMUX_X0Y5 Î D
BUFGMUX_X0Y4 Î C
P P9
F3
P14 P22
H5
J5
K3
M5 Î LHCLK0
N P10
F2
P15 P23
H6
J4
K2
L5 Î LHCLK1
P P11
F1
P16 P24
H3
J1
K7
L8
Î LHCLK2
DCM_X0Y2
N P12
G1
P17 P25
H4
J2
L7
M8 Î LHCLK3
BUFGMUX_X0Y3 Î B
BUFGMUX_X0Y2 Î A
BUFGMUX_X0Y9 Î H
BUFGMUX_X0Y8 Î G
P P15
G3
P20 P28
J2
K3
M1
M1 Î LHCLK4
N P16
H1
P21 P29
J3
K4
L1
N1 Î LHCLK5
P P17
H2
P22 P30
J5
K6
M3
M3 Î LHCLK6
DCM_X0Y1
N P18
H3
P23 P31
J4
K5
L3
M4 Î LHCLK7
BUFGMUX_X0Y7 Î F
BUFGMUX_X0Y6 Î E
Table 32: Direct Clock Input and Optional External Feedback to Right-Edge DCMs (XC3S1200E and XC3S1600E)
Right Edge
DCM/BUFGMUX RHCLK
D Í BUFGMUX_X3Y5
C Í BUFGMUX_X3Y4
Single-Ended Pin Number by Package Type
Diff.
VQ100 CP132 TQ144 PQ208 FT256 FG320 FG400 FG484 ^Clock
RHCLK7 Í P68 G13
P94 P135 H11
J14
J20
L19 N
DCM_X3Y2
RHCLK6 Í P67
G14
P93 P134 H12
J15
K20
L18 P
RHCLK5 Í P66
H12
P92 P133 H14
J16
K14
L21 N
RHCLK4 Í P65
H13
P91 P132 H15
J17
K13
L20 P
B Í BUFGMUX_X3Y3
A Í BUFGMUX_X3Y2
H Í BUFGMUX_X3Y9
G Í BUFGMUX_X3Y8
RHCLK3 Í P63
J14
P88 P129 J13
K14
L14
M16 N
DCM_X3Y1
RHCLK2 Í P62
J13
P87 P128 J14
K15
L15
M15 P
RHCLK1 Í P61
J12
P86 P127 J16
K12
L16
M22 N
RHCLK0 Í P60
K14
P85 P126 K16
K13
M16
N22 P
F Í BUFGMUX_X3Y7
E Í BUFGMUX_X3Y6
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DS312-2 (v3.4) November 9, 2006
Product Specification