XC3S100E_06 Datasheet, PDF (229/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

R
FG484 Footprint
Left Half of Package
(top view)
214
I/O: Unrestricted,
general-purpose user I/O
INPUT: User I/O or
72 reference resistor input for
bank
46
DUAL: Configuration pin,
then possible user I/O
28
VREF: User I/O or input
voltage reference for bank
16
CLK: User I/O, input, or
clock buffer input
2
CONFIG: Dedicated
configuration pins
4
JTAG: Dedicated JTAG
port pins
48 ^{GND: Ground}
28
VCCO: Output voltage
supply for bank
16
VCCINT: Internal core
supply voltage (+1.2V)
10
VCCAUX: Auxiliary supply
voltage (+2.5V)
0 ^{N.C.: Not connected}
Pinout Descriptions
1
A GND
Bank 0
2
3
4
5
6
7
8
9
10
INPUT INPUT I/O
I/O
I/O
I/O
I/O
I/O
I/O
L37P_0 L37N_0 L35N_0 L35P_0 L33N_0 L33P_0 L30P_0 L24N_0 L24P_0
11
GND
B PROG_B TDI
C
I/O
L01N_3
I/O
L01P_3
D
I/O
L04P_3
I/O
L02N_3
VREF_3
I/O
L39P_0
GND
I/O
L02P_3
I/O _{VCCO_0 I/O}
L39N_0
I/O
I/O ^INPUT
L40P_0
L34P_0
I/O
L40N_0
HSWAP
I/O
L38P_0
I/O
L38N_0
VREF_0
GND
INPUT
L34N_0
I/O
L36P_0
I/O
L30N_0
INPUT
L31N_0
INPUT
L31P_0
I/O
L28P_0
I/O
L28N_0
I/O
L29P_0
I/O
VCCO_0 L21N_0
GCLK11
I/O
L25P_0
I/O
L21P_0
GCLK10
I/O
L25N_0
VREF_0
I/O
L22N_0
E
I/O _{VCCO_3} I/O
L04N_3
L03N_3
I/O _{VCCAUX INPUT}
L03P_3
I/O _{VCCO_0} I/O
L36N_0
L29N_0
GND
I/O
L22P_0
F
I/O
L07N_3
INPUT
I/O
L05P_3
I/O
L05N_3
INPUT
GND
I/O
L32N_0
VREF_0
I/O
L32P_0
I/O
INPUT INPUT
L23N_0 L23P_0
G
I/O
L07P_3
GND
INPUT
I/O
L06P_3
I/O
L06N_3
I/O
L08N_3
VREF_3
I/O
L08P_3
I/O
INPUT INPUT _{VCCO_0}
L26N_0 L26P_0
H
I/O
L11N_3
I/O
L10N_3
I/O
L10P_3
I/O
L09N_3
I/O _{VCCO_3 INPUT}
L09P_3
I/O
L27N_0
I/O
L27P_0
I/O
INPUT
L20N_0
GCLK9
J
I/O
L11P_3
VCCO_3
I/O
L13N_3
VREF_3
GND
I/O
I/O _INPUT I/O
L12P_3 L12N_3
L14N_3
GND VCCINT
I/O
K
I/O
L16N_3
INPUT
I/O
L13P_3
I/O
L15N_3
I/O
L15P_3
INPUT
I/O
L17P_3
I/O _VCCINT
L14P_3
GND
VCCINT
L
I/O
L16P_3
I/O
M
L20P_3
LHCLK4
TRDY2
I/O
N L20N_3
LHCLK5
GND
INPUT
VCCO_3
INPUT
VREF_3
VCCAUX
I/O
L18N_3
LHCLK1
I/O
L21P_3
LHCLK6
I/O
L21N_3
LHCLK7
I/O
L18P_3
LHCLK0
INPUT
I/O
L24N_3
VREF_3
I/O
L24P_3
GND
INPUT
I/O
L22N_3
I/O
L17N_3
VCCO_3
I/O
L22P_3
I/O
L19P_3
LHCLK2
GND VCCINT VCCINT
I/O
L19N_3 _VCCINT
LHCLK3
IRDY2
GND
VCCINT
I/O _{VCCAUX VCCINT GND}
L23P_3
P
I/O
L25P_3
I/O
L25N_3
INPUT
GND
I/O
I/O
I/O
I/O
L27P_3 L27N_3 L26P_3 L23N_3
GND
I/O
L17P_2
GND
R
I/O
L28P_3
T INPUT
U
I/O
L31P_3
V
I/O
L33P_3
W
I/O
L33N_3
Y
I/O
L37P_3
A I/O
A ^L38N_3
I/O
I/O
L28N_3 L29N_3
GND ^INPUT
VREF_3
I/O
I/O
L31N_3 L34P_3
VCCO_3 ^I/O
L35P_3
I/O
L36P_3
I/O
L36N_3
VREF_3
I/O
GND
L37N_3
I/O
L38P_3
I/O
L01P_2
CSO_B
I/O _{VCCO_3} I/O
L29P_3
L30P_3
I/O
I/O
I/O
L32N_3 L32P_3 L30N_3
I/O _{INPUT GND}
L34N_3
I/O _VCCAUX I/O
L35N_3
L04P_2
INPUT
INPUT
L02P_2
I/O
L03P_2
DOUT
BUSY
I/O
L03N_2
MOSI
CSI_B
I/O
L04N_2
INPUT
L05N_2
INPUT _{VCCO_2} INPUT
L02N_2
L05P_2
I/O
L26N_3
INPUT
I/O
L07N_2
I/O
L07P_2
I/O
L06N_2
I/O
L06P_2
GND
INPUT
I/O
L13N_2
VREF_2
I/O
I/O
L10N_2 L13P_2
I/O _{VCCO_2}
L10P_2
I/O
L09N_2
VREF_2
I/O
L12P_2
I/O
I/O
L09P_2 L12N_2
I/O
I/O
I/O _{VCCO_2}
L11P_2
I/O
L17N_2
I/O
L16P_2
I/O
L16N_2
GND
I/O
L20P_2
D4
GCLK14
I/O
L20N_2
D3
GCLK15
I/O
L19N_2
D6
GCLK13
I/O
L19P_2
D7
GCLK12
INPUT _VCCAUX
L15P_2
INPUT INPUT
L15N_2 L18P_2
INPUT
I/O L18N_2
VREF_2
A
I/O
GND INPUT L01N_2
I/O
I/O ^{INPUT INPUT I/O}
I/O
I/O
I/O
B
INIT_B ^VREF_2
L08P_2 L08N_2 L11N_2 L14N_2 L14P_2
D5
Bank 2
Figure 89: FG484 Package Footprint (top view)
DS312_10_101905
DS312-4 (v3.4) November 9, 2006
www.xilinx.com
229
Product Specification