XC3S100E_06 Datasheet, PDF (88/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

Functional Description
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Table 58: Byte-Wide Peripheral Interface (BPI) Connections (Continued)
Pin Name FPGA Direction
Description
During Configuration
After Configuration
HDC
Output
PROM Write Enable
Connect to PROM write-enable
input (WE#). FPGA drives this
signal High throughout
configuration.
User I/O
LDC2
D
Output
PROM Byte Mode
This signal is not used for x8
PROMs. For PROMs with a x8/x16
data width control, connect to
PROM byte-mode input (BYTE#).
See Precautions Using x8/x16
Flash PROMs. FPGA drives this
signal Low throughout
configuration.
User I/O. Drive this pin
High after configuration to
use a x8/x16 PROM in x16
mode.
A[23:0]
Output
Address
Connect to PROM address inputs.
High-order address lines may not
be available in all packages and
not all may be required. Number of
address lines required depends
on the size of the attached Flash
PROM. FPGA address generation
controlled by M0 mode pin.
Addresses presented on falling
CCLK edge.
Only 20 address lines are
available in TQ144 package.
User I/O
D[7:0]
Input
Data Input
FPGA receives byte-wide data on
these pins in response the
address presented on A[23:0].
Data captured by FPGA
User I/O. If bitstream
option Persist=Yes,
becomes part of
SelectMap parallel
peripheral interface.
CSO_B
Output
Chip Select Output. Active Low.
Not used in single FPGA
applications. In a daisy-chain
configuration, this pin connects to
the CSI_B pin of the next FPGA in
the chain. If HSWAP = 1 in a
multi-FPGA daisy-chain
application, connect this signal to
a 4.7 kΩ pull-up resistor to
VCCO_2. Actively drives Low
when selecting a downstream
device in the chain.
User I/O
BUSY
Output
Busy Indicator. Typically only
used after configuration, if
bitstream option Persist=Yes.
Not used during configuration but
actively drives.
User I/O. If bitstream
option Persist=Yes,
becomes part of
SelectMap parallel
peripheral interface.
CCLK
Output
Configuration Clock. Generated
by FPGA internal oscillator.
Frequency controlled by
ConfigRate bitstream generator
option. If CCLK PCB trace is long or
has multiple connections, terminate
this output to maintain signal
integrity. See CCLK Design
Considerations.
Not used in single FPGA
applications but actively drives. In
a daisy-chain configuration, drives
the CCLK inputs of all other
FPGAs in the daisy-chain.
User I/O. If bitstream
option Persist=Yes,
becomes part of
SelectMap parallel
peripheral interface.
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DS312-2 (v3.4) November 9, 2006
Product Specification