XC3S100E_06 Datasheet, PDF (181/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

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Table 136: TQ144 Package Pinout (Continued)
Bank
XC3S100E Pin Name
3
IO
IP
XC3S250E Pin Name
3
3
3
3
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
IP
IP/VREF_3
VCCO_3
VCCO_3
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
DONE
PROG_B
TCK
TDI
TDO
TMS
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
IP
IP/VREF_3
VCCO_3
VCCO_3
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
DONE
PROG_B
TCK
TDI
TDO
TMS
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
Pinout Descriptions
TQ144 Pin
P29
P36
P12
P13
P28
P11
P19
P27
P37
P46
P55
P61
P73
P90
P99
P118
P127
P133
P72
P1
P110
P144
P109
P108
P30
P65
P102
P137
P9
P45
P80
P115
Type
100E: I/O
250E: INPUT
INPUT
VREF
VCCO
VCCO
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
CONFIG
CONFIG
JTAG
JTAG
JTAG
JTAG
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
DS312-4 (v3.4) November 9, 2006
www.xilinx.com
181
Product Specification