XC3S100E_06 Datasheet, PDF (49/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

R
Functional Description
CLKIN
Delay
1
Delay
2
Delay
n-1
Delay
n
Control
CLK0
CLK90
CLK180
CLK270
CLK2X
CLK2X180
CLKDV
LOCKED
CLKFB
RST
Phase
Detection
DS099-2_08_041103
Figure 41: Simplified Functional Diagram of DLL
Table 28: DLL Signals
Signal
Direction
CLKIN
Input
CLKFB
Input
CLK0
CLK90
CLK180
CLK270
CLK2X
CLK2X180
Output
Output
Output
Output
Output
Output
CLKDV
Output
Description
Receives the incoming clock signal. See Table 30, Table 31, and Table 32 for optimal
external inputs to a DCM.
Accepts either CLK0 or CLK2X as the feedback signal. (Set the CLK_FEEDBACK
attribute accordingly).
Generates a clock signal with the same frequency and phase as CLKIN.
Generates a clock signal with the same frequency as CLKIN, phase-shifted by 90°.
Generates a clock signal with the same frequency as CLKIN, phase-shifted by 180°.
Generates a clock signal with the same frequency as CLKIN, phase-shifted by 270°.
Generates a clock signal with the same phase as CLKIN, and twice the frequency.
Generates a clock signal with twice the frequency of CLKIN, and phase-shifted 180°
with respect to CLK2X.
Divides the CLKIN frequency by CLKDV_DIVIDE value to generate lower frequency
clock signal that is phase-aligned to CLKIN.
Delay-Locked Loop (DLL)
The most basic function of the DLL component is to elimi-
nate clock skew. The main signal path of the DLL consists of
an input stage, followed by a series of discrete delay ele-
ments or steps, which in turn leads to an output stage. This
path together with logic for phase detection and control
forms a system complete with feedback as shown in
Figure 41. In Spartan-3E FPGAs, the DLL is implemented
using a counter-based delay line.
The DLL component has two clock inputs, CLKIN and
CLKFB, as well as seven clock outputs, CLK0, CLK90,
CLK180, CLK270, CLK2X, CLK2X180, and CLKDV as
described in Table 28. The clock outputs drive simulta-
neously. Signals that initialize and report the state of the
DLL are discussed in Status Logic.
The clock signal supplied to the CLKIN input serves as a
reference waveform. The DLL seeks to align the rising-edge
of feedback signal at the CLKFB input with the rising-edge
of CLKIN input. When eliminating clock skew, the common
approach to using the DLL is as follows: The CLK0 signal is
passed through the clock distribution network that feeds all
the registers it synchronizes. These registers are either
internal or external to the FPGA. After passing through the
clock distribution network, the clock signal returns to the
DLL via a feedback line called CLKFB. The control block
DS312-2 (v3.4) November 9, 2006
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49
Product Specification