XC3S100E_06 Datasheet, PDF (40/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

Functional Description
R
Block RAM Attribute Definitions
A block RAM has a number of attributes that control its
behavior as shown in Table 24.
Table 24: Block RAM Attributes
Function
Attribute
Possible Values
Initial Content for Data Memory, Loaded
INITxx
Each initialization string defines 32 hex values of
during Configuration
(INIT_00 through INIT3F) the 16384-bit data memory of the block RAM.
Initial Content for Parity Memory, Loaded
INITPxx
Each initialization string defines 32 hex values of
during Configuration
(INITP_00 through INITP0F) the 2048-bit parity data memory of the block
RAM.
Data Output Latch Initialization
INIT (single-port)
Hex value the width of the chosen port.
INITA, INITB (dual-port)
Data Output Latch Synchronous
Set/Reset Value
SRVAL (single-port)
SRVAL_A, SRVAL_B
(dual-port)
Hex value the width of the chosen port.
Data Output Latch Behavior during Write
(see Block RAM Data Operations)
WRITE_MODE
WRITE_FIRST, READ_FIRST, NO_CHANGE
Block RAM Data Operations
Writing data to and accessing data from the block RAM are
synchronous operations that take place independently on
each of the two ports. Table 25 describes the data opera-
tions of each port as a result of the block RAM control sig-
nals in their default active-High edges.
The waveforms for the write operation are shown in the top
half of Figure 33, Figure 34, and Figure 35. When the WE
and EN signals enable the active edge of CLK, data at the
DI input bus is written to the block RAM location addressed
by the ADDR lines.
Table 25: Block RAM Function Table
Input Signals
Output Signals
GSR EN SSR WE CLK ADDR DIP DI
DOP
DO
Immediately After Configuration
Loaded During Configuration
X
X
Global Set/Reset Immediately After Configuration
1
X
X
X
X
X
X
X
INIT
INIT
RAM Disabled
0
0
X
X
X
X
X
X
No Chg
No Chg
Synchronous Set/Reset
0
1
1
0↑
X
X
X
SRVAL
SRVAL
Synchronous Set/Reset During Write RAM
0
1
1
1↑
addr pdata Data SRVAL
SRVAL
Read RAM, no Write Operation
0
1
0
0↑
addr X
X RAM(pdata) RAM(data)
RAM Data
Parity
Data
INITP_xx
INIT_xx
No Chg
No Chg
No Chg
No Chg
No Chg
No Chg
RAM(addr) RAM(addr)
← pdata
← data
No Chg
No Chg
40
www.xilinx.com
DS312-2 (v3.4) November 9, 2006
Product Specification