XC3S100E_06 Datasheet, PDF (75/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

R
Functional Description
+1.2V
VCCINT
P
HSWAP
VCCO_0
Serial Master
Mode
‘0’
M2
‘0’
M1
‘0’
M0
VCCO_2
DIN
CCLK
DOUT
INIT_B
+2.5V
JTAG
TDI
TMS
TCK
TDO
Spartan-3E
FPGA
TDI
TMS
TCK
VCCAUX
TDO
PROG_B
DONE
GND
VCCO_0
V
+2.5V
XCFxxS = +3.3V
XCFxxP = +1.8V
VCCINT
D0
VCCO
V
CLK
OE/RESET
Platform Flash
XCFxx
CE
CEO
CF
VCCJ
+2.5V
TDI
TDO
TMS
TCK
GND
+2.5V
V
+1.2V
P
Slave
Serial
Mode
‘1’
‘1’
‘1’
VCCINT
HSWAP
VCCO_0
VCCO_2
M2
DOUT
M1
INIT_B
M0
Spartan-3E
CCLK ^FPGA
DIN
TDI
TMS
TCK
VCCAUX
TDO
PROG_B
GND
DONE
VCCO_0
V
+2.5V
CCLK
DOUT
PROG_B
Recommend
open-drain
driver
PROG_B
TCK
TMS
DONE
INIT_B
Figure 52: Daisy-Chaining from Master Serial Mode
DS312-2_45_102105
Daisy-Chaining
If the application requires multiple FPGAs with different con-
figurations, then configure the FPGAs using a daisy chain,
as shown in Figure 52. Use Master Serial mode
(M[2:0] = <0:0:0>) for the FPGA connected to the Platform
Flash PROM and Slave Serial mode (M[2:0] = <1:1:1>) for
all other FPGAs in the daisy-chain. After the master
FPGA—the FPGA on the left in the diagram—finishes load-
ing its configuration data from the Platform Flash, the mas-
ter device supplies data using its DOUT output pin to the
next device in the daisy-chain, on the falling CCLK edge.
JTAG Interface
Both the Spartan-3E FPGA and the Platform Flash PROM
have a four-wire IEEE 1149.1/1532 JTAG port. Both devices
share the TCK clock input and the TMS mode select input.
The devices may connect in either order on the JTAG chain
with the TDO output of one device feeding the TDI input of
the following device in the chain. The TDO output of the last
device in the JTAG chain drives the JTAG connector.
The JTAG interface on Spartan-3E FPGAs is powered by
the 2.5V V_CCAUX supply. Consequently, the PROM’s V_CCJ
supply input must also be 2.5V. To create a 3.3V JTAG
interface, please refer to application note XAPP453: The
3.3V Configuration of Spartan-3 FPGAs for additional infor-
mation.
In-System Programming Support
Both the FPGA and the Platform Flash PROM are in-sys-
tem programmable via the JTAG chain. Download support
is provided by the Xilinx iMPACT programming software
and the associated Xilinx Parallel Cable IV, MultiPRO, or
Platform Cable USB programming cables.
Storing Additional User Data in Platform Flash
After configuration, the FPGA application can continue to
use the Master Serial interface pins to communicate with
the Platform Flash PROM. If desired, use a larger Platform
Flash PROM to hold additional non-volatile application
data, such as MicroBlaze processor code, or other user
data such as serial numbers and Ethernet MAC IDs. The
FPGA first configures from Platform Flash PROM. Then
using FPGA logic after configuration, the FPGA copies
MicroBlaze code from Platform Flash into external DDR
SDRAM for code execution.
See XAPP694: Reading User Data from Configuration
PROMs and XAPP482: MicroBlaze Platform Flash/PROM
Boot Loader and User Data Storage for specific details on
how to implement such an interface.
SPI Serial Flash Mode
In SPI Serial Flash mode (M[2:0] = <0:0:1>), the Spartan-3E
FPGA configures itself from an attached industry-standard
SPI serial Flash PROM, as illustrated in Figure 53 and
Figure 54. The FPGA supplies the CCLK output clock from
its internal oscillator to the clock input of the attached SPI
Flash PROM.
DS312-2 (v3.4) November 9, 2006
www.xilinx.com
75
Product Specification