XC3S100E_06 Datasheet, PDF (198/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

Pinout Descriptions
R
User I/Os by Bank
Table 143, Table 144, and Table 145 indicate how the avail-
able user-I/O pins are distributed between the four I/O
banks on the FT256 package.
The XC3S250E FPGA in the FT256 package has 18 uncon-
nected balls, labeled with an “N.C.” type. These pins are
also indicated with the black diamond (‹) symbol in
Figure 86.
Table 143: User I/Os Per Bank on XC3S250E in the FT256 Package
Package
Maximum
Edge
I/O Bank
I/O
I/O
All Possible I/O Pins by Type
INPUT
DUAL
VREF
Top
0
44
20
10
1
5
Right
1
42
10
7
21
4
Bottom
2
44
8
9
24
3
Left
3
42
24
7
0
3
TOTAL
172
62
33
46
15
CLK
8
0⁽¹⁾
0⁽¹⁾
8
16
Notes:
1. The eight global clock pins in this bank have optional functionality during configuration and are counted in the DUAL column.
Table 144: User I/Os Per Bank on XC3S500E in the FT256 Package
Package
Maximum
Edge
I/O Bank
I/O
I/O
All Possible I/O Pins by Type
INPUT
DUAL
VREF
Top
0
46
22
10
1
5
Right
1
48
15
7
21
5
Bottom
2
48
11
9
24
4
Left
3
48
28
7
0
5
TOTAL
190
76
33
46
19
CLK
8
0⁽¹⁾
0⁽¹⁾
8
16
Notes:
1. The eight global clock pins in this bank have optional functionality during configuration and are counted in the DUAL column.
.
Table 145: User I/Os Per Bank on XC3S1200E in the FT256 Package
Package
Maximum
Edge
I/O Bank
I/O
I/O
All Possible I/O Pins by Type
INPUT
DUAL
VREF
Top
0
46
24
8
1
5
Right
1
48
14
8
21
5
Bottom
2
48
13
7
24
4
Left
3
48
27
8
0
5
TOTAL
190
78
31
46
19
CLK
8
0⁽¹⁾
0⁽¹⁾
8
16
Notes:
1. The eight global clock pins in this bank have optional functionality during configuration and are counted in the DUAL column.
198
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DS312-4 (v3.4) November 9, 2006
Product Specification