XC3S100E_06 Datasheet, PDF (45/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

R
Functional Description
A[17:0]
B[17:0]
CEA
CEB
CEP
CLK
RSTA
RSTB
RSTP
BCIN[17:0]
MULT18X18SIO
P[35:0]
BCOUT[17:0]
DS312-2_28_021205
Figure 37: MULT18X18SIO Primitive
Cascading Multipliers
The MULT18X18SIO primitive has two additional ports
called BCIN and BCOUT to cascade or share the multi-
plier’s ‘B’ input among several multiplier bocks. The 18-bit
BCIN “cascade” input port offers an alternate input source
from the more typical ‘B’ input. The B_INPUT attribute spec-
ifies whether the specific implementation uses the BCIN or
‘B’ input path. Setting B_INPUT to DIRECT chooses the ‘B’
input. Setting B_INPUT to CASCADE selects the alternate
BCIN input. The BREG register then optionally holds the
selected input value, if required.
BCOUT is an 18-bit output port that always reflects the
value that is applied to the multiplier’s second input, which is
either the ‘B’ input, the cascaded value from the BCIN input,
or the output of the BREG if it is inserted.
Figure 38 illustrates the four possible configurations using
different settings for the B_INPUT attribute and the BREG
attribute.
CEB
BCOUT[17:0]
BREG
X
CE
D
Q
BCOUT[17:0]
X
CLK
RST
RSTB
BREG = 1
B_INPUT = CASCADE
BCIN[17:0]
BREG = 0
B_INPUT = CASCADE
BCIN[17:0]
CEB
B[17:0]
CLK
RSTB
BCOUT[17:0]
BCOUT[17:0]
BREG
X
X
CE
D
Q
B[17:0]
RST
BREG = 0
B_INPUT = DIRECT
BREG = 1
B_INPUT = DIRECT
DS312-2_29_021505
Figure 38: Four Configurations of the B Input
DS312-2 (v3.4) November 9, 2006
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