XC3S100E_06 Datasheet, PDF (94/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

Functional Description
R
successful, the FPGA then triggers a MultiBoot event, caus-
ing the FPGA to reconfigure from the opposite end of the
Flash PROM memory. This second configuration contains
the FPGA application for normal operation.
Parallel Flash PROM
FFFFFF
Similarly, the general FPGA application could trigger
another MultiBoot event at any time to reload the diagnos-
tics design, and so on.
Parallel Flash PROM
FFFFFF
General
FPGA
Application
STARTUP_SPARTAN3E
General
FPGA
Application
User Area
Di agnostics
FPGA
Application
> 300 ns
GSR
GTS
MBT
CLK
User Area
Reconfigure
Di agnostics
FPGA
Application
0
0
First Configuration
Second Configuration
DS312-2_51_103105
Figure 60: Use MultiBoot to Load Alternate Configuration Images
In another potential application, the initial design loaded into
the FPGA image contains a “golden” or “fail-safe” configura-
tion image, which then communicates with the outside
world and checks for a newer image. If there is a new con-
figuration revision and the new image verifies as good, the
“golden” configuration triggers a MultiBoot event to load the
new image.
When a MultiBoot event is triggered, the FPGA then again
drives its configuration pins as described in Table 58. How-
ever, the FPGA does not assert the PROG_B pin. The sys-
tem design must ensure that no other device drives on
these same pins during the reconfiguration process. The
FPGA’s DONE, LDC[2:0], or HDC pins can temporarily dis-
able any conflicting drivers during reconfiguration.
Asserting the PROG_B pin Low overrides the MultiBoot fea-
ture and forces the FPGA to reconfigure starting from the
end of memory defined by the mode pins, shown in
Table 57.
94
www.xilinx.com
DS312-2 (v3.4) November 9, 2006
Product Specification