XC3S100E_06 Datasheet, PDF (169/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

R
Pinout Descriptions
User I/Os by Bank
Table 131 indicates how the 66 available user-I/O pins are
distributed between the four I/O banks on the VQ100 pack-
age.
Table 131: User I/Os Per Bank for XC3S100E and XC3S250E in the VQ100 Package
Package
Maximum
Edge I/O Bank
I/O
I/O
All Possible I/O Pins by Type
INPUT
DUAL
VREF
Top
0
15
5
0
1
1
Right
1
15
6
0
0
1
Bottom
2
19
0
0
18
1
Left
3
17
5
1
2
1
TOTAL
66
16
1
21
4
CLK
8
8
0⁽¹⁾
8
24
Notes:
1. The eight global clock pins in this bank have optional functionality during configuration and are counted in the DUAL column.
Footprint Migration Differences
The production XC3S100E and XC3S250E FPGAs have
identical footprints in the VQ100 package. Designs can
migrate between the XC3S100E and XC3S250E without
further consideration.
DS312-4 (v3.4) November 9, 2006
www.xilinx.com
169
Product Specification