XC3S100E_06 Datasheet, PDF (156/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

R
DC and Switching Characteristics
Byte Peripheral Interface (BPI) Configuration Timing
PROG_B
(Input)
HSWAP
(Input)
CSI_B
(Input)
RDWR_B
(Input)
M[2:0]
(Input)
INIT_B
(Open-Drain)
LDC[2:0]
HSWAP must be stable before INIT_B goes High and remain constant throughout configuration.
T_MINIT
<0:1:1>
T_INITM
Mode input pins M[2:0] are sampled when INIT_B goes High. After this point,
input values do not matter until DONE goes High, at which point the mode pins
become user-I/O pins.
Pin initially pulled High by internal pull-up resistor if HSWAP input is Low.
Pin initially high-impedance (Hi-Z) if HSWAP input is High.
HDC
CSO_B
New ConfigRate active
CCLK
A[23:0]
D[7:0]
(Input)
T_CCLK1
T _INITADDR
0x00_0000
0x00_0001
Byte 0
Byte 1
T_CCLK1
T_CCLKn
T_CCO
Address
Address Address
T_AVQV
Data
T_DCC
Data
Data
T_CCD
Data
Shaded values indicate specifications on attached parallel NOR Flash PROM.
UG332_c5_08_110206
Figure 78: Waveforms for Byte-wide Peripheral Interface (BPI) Configuration (BPI-DN mode shown)
Table 119: Timing for Byte-wide Peripheral Interface (BPI) Configuration Mode
Symbol
Description
T_CCLK1
T_CCLKn
T_MINIT
Initial CCLK clock period
CCLK clock period after FPGA loads ConfigRate setting
Setup time on CSI_B, RDWR_B, and M[2:0] mode pins before the rising
edge of INIT_B
T_INITM
Hold time on CSI_B, RDWR_B, and M[2:0] mode pins after the rising
edge of INIT_B
T_INITADDR Minimum period of initial A[23:0] address cycle;
LDC[2:0] and HDC are asserted and valid
BPI-UP:
(M[2:0]=<0:1:0>)
BPI-DN:
(M[2:0]=<0:1:1>)
Minimum Maximum Units
(see Table 111)
(see Table 111)
50
-
ns
0
-
ns
5
5
T_CCLK1
cycles
2
2
156
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DS312-3 (v3.4) November 9, 2006
Product Specification