XC3S100E_06 Datasheet, PDF (151/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

R
Master Serial and Slave Serial Mode Timing
PROG_B
(Input)
DC and Switching Characteristics
INIT_B
(Open-Drain)
CCLK
(Input/Output)
DIN
(Input)
DOUT
(Output)
T_DCC
T_CCD
Bit 0
Bit 1
T_MCCL
T_SCCL
T_MCCH
T_SCCH
1/F_CCSER
Bit n Bit n+1
T_CCO
Bit n-64 Bit n-63
Figure 75: Waveforms for Master Serial and Slave Serial Configuration
DS312-3_05_103105
Table 115: Timing for the Master Serial and Slave Serial Configuration Modes
Symbol
Description
Clock-to-Output Times
T_CCO
The time from the falling transition on the CCLK pin to data
appearing at the DOUT pin
Setup Times
T_DCC
The time from the setup of data at the DIN pin to the active edge of
the CCLK pin
Hold Times
T_CCD
The time from the active edge of the CCLK pin to the point when
data is last held at the DIN pin
Clock Timing
T_CCH
High pulse width at the CCLK input pin
T_CCL
Low pulse width at the CCLK input pin
F_CCSER
Frequency of the clock signal at
the CCLK input pin
No bitstream compression
With bitstream compression
Slave/
Master
Both
Both
Both
Master
Slave
Master
Slave
Slave
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 76.
2. For serial configuration with a daisy-chain of multiple FPGAs, the maximum limit is 25 MHz.
All Speed Grades
Min
Max Units
1.5
10.0
ns
11.0
-
ns
0
-
ns
See Table 113
See Table 114
See Table 113
See Table 114
0
66⁽²⁾ MHz
0
20
MHz
DS312-3 (v3.4) November 9, 2006
www.xilinx.com
151
Product Specification