XC3S100E_06 Datasheet, PDF (159/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

R
DC and Switching Characteristics
Revision History
The following table shows the revision history for this document.
Date
03/01/05
11/23/05
03/22/06
04/07/06
05/19/06
05/30/06
11/09/06
Version
1.0
2.0
3.0
3.1
3.2
3.2.1
3.4
Revision
Initial Xilinx release.
Added AC timing information and additional DC specifications.
Upgraded data sheet status to Preliminary. Finalized production timing parameters. All
speed grades for all Spartan-3E FPGAs are now Production status using the v1.21 speed
files, as shown in Table 83. Expanded description in Note 2, Table 77. Updated pin-to-pin
and clock-to-output timing based on final characterization, shown in Table 85. Updated
system-synchronous input setup and hold times based on final characterization, shown in
Table 86 and Table 87. Updated other I/O timing in Table 89. Provided input and output
adjustments for LVPECL_25, DIFF_SSTL and DIFF_HSTL I/O standards that supersede
the v1.21 speed file values, in Table 90 and Table 93. Reduced I/O three-state and set/reset
delays in Table 92. Added XC3S100E FPGA in CP132 package to Table 95. Increased T_AS
slice flip-flop timing by 100 ps in Table 97. Updated distributed RAM timing in Table 98 and
SRL16 timing in Table 99. Updated global clock timing, removed left/right clock buffer limits
in Table 100. Updated block RAM timing in Table 102. Added DCM parameters for
remainder of Step 0 device; added improved Step 1 DCM performance to Table 103,
Table 104, Table 105, and Table 106. Added minimum INIT_B pulse width specification,
T_INIT, in Table 110. Increased data hold time for Slave Parallel mode to 1.0 ns (T_SMCCD) in
Table 116. Improved the DCM performance for the XC3S1200E, Stepping 0 in Table 103,
Table 104, Table 105, and Table 106. Corrected links in Table 117 and Table 119. Added
MultiBoot timing specifications to Table 121.
Improved SSO limits for LVDS_25, MINI_LVDS_25, and RSDS_25 I/O standards in the QFP
packages (Table 96). Removed potentially confusing Note 2 from Table 77.
Clarified that 100 mV of hysteresis applies to LVCMOS33 and LVCMOS25 I/O standards
(Note 4, Table 79). Other minor edits.
Corrected various typos and incorrect links.
Improved absolute maximum voltage specifications in Table 72, providing additional
overshoot allowance. Widened the recommended voltage range for PCI and PCI-X
standards in Table 79. Clarified Note 2, Table 82. Improved various timing specifications for
v1.26 speed file. Added Table 84 to summarize the history of speed file releases after which
time all devices became Production status. Added absolute minimum values for Table 85,
Table 91, and Table 92. Updated pin-to-pin setup and hold timing based on default
IFD_DELAY_VALUE settings in Table 86, Table 87, and Table 89. Added Table 88 about
source-synchronous input capture sample window. Promoted Module 3 to Production
status. Synchronized all modules to v3.4.
DS312-3 (v3.4) November 9, 2006
www.xilinx.com
159
Product Specification