XC3S100E_06 Datasheet, PDF (150/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

R
DC and Switching Characteristics
Configuration Clock (CCLK) Characteristics
Table 111: Master Mode CCLK Output Period by ConfigRate Option Setting
Symbol
Description
ConfigRate
Setting
Temperature
Range
T_CCLK1
CCLK clock period by
ConfigRate setting
1
Commercial
(power-on value) _Industrial
T_CCLK3
Commercial
3
Industrial
T_CCLK6
Commercial
6
Industrial
T_CCLK12
Commercial
12
Industrial
T_CCLK25
Commercial
25
Industrial
T_CCLK50
Commercial
50
Industrial
Minimum
570
485
285
242
142
121
71.2
60.6
35.5
30.3
17.8
15.1
Maximum
1,250
625
313
157
78.2
39.1
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
1. Set the ConfigRate option value when generating a configuration bitstream. See Bitstream Generator (BitGen) Options in Module 2.
Table 112: Master Mode CCLK Output Frequency by ConfigRate Option Setting
Symbol
Description
ConfigRate
Setting
Temperature
Range
Minimum
F_CCLK1
Equivalent CCLK clock
frequency by ConfigRate
1
Commercial
(power-on value) _Industrial
0.8
setting
Commercial
F_CCLK3
3
1.6
Industrial
F_CCLK6
Commercial
6
3.2
Industrial
F_CCLK12
Commercial
12
6.4
Industrial
F_CCLK25
Commercial
25
12.8
Industrial
F_CCLK50
Commercial
50
25.6
Industrial
Maximum
1.8
2.1
3.6
4.2
7.1
8.3
14.1
16.5
28.1
33.0
56.2
66.0
Units
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Table 113: Master Mode CCLK Output Minimum Low and High Time
Symbol
Description
ConfigRate Setting
1
3
6
12
25
T_MCCL,
T_MCCH
Master mode CCLK minimum Commercial
Low and High time
Industrial
276 138 69 34.5 17.1
235 117 58 29.3 14.5
Units
50
8.5
ns
7.3
ns
Table 114: Slave Mode CCLK Input Low and High Time
Symbol
Description
T_SCCL,
T_SCCH
CCLK Low and High time
Min
Max
Units
5
∞
ns
150
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DS312-3 (v3.4) November 9, 2006
Product Specification