XC3S100E_06 Datasheet, PDF (135/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

R
DC and Switching Characteristics
Table 94: Test Methods for Timing Measurement at I/Os (Continued)
Signal Standard
(IOSTANDARD)
DIFF_HSTL_I_18
DIFF_HSTL_III_18
DIFF_SSTL18_I
DIFF_SSTL2_I
V_REF (V)
0.9
1.1
0.9
1.25
Inputs
V_L (V)
V_REF – 0.5
V_REF – 0.5
V_REF – 0.5
V_REF – 0.5
V_H (V)
V_REF + 0.5
V_REF + 0.5
V_REF + 0.5
V_REF + 0.5
Outputs
R_T (Ω)
50
V_T (V)
0.9
50
1.8
50
0.9
50
1.25
Notes:
1. Descriptions of the relevant symbols are as follows:
V_REF – The reference voltage for setting the input switching threshold
V_ICM – The common mode input voltage
V_M – Voltage of measurement point on signal transition
V_L – Low-level test voltage at Input pin
V_H – High-level test voltage at Input pin
R_T – Effective termination resistance, which takes on a value of 1MΩ when no parallel termination is required
V_T – Termination voltage
2. The load capacitance (C_L) at the Output pin is 0 pF for all signal standards.
3. According to the PCI specification.
Inputs and
Outputs
V_M (V)
V_REF
V_REF
V_REF
V_REF
The capacitive load (C_L) is connected between the output
and GND. The Output timing for all standards, as published
in the speed files and the data sheet, is always based on a
C_L value of zero. High-impedance probes (less than 1 pF)
are used for all measurements. Any delay that the test fix-
ture might contribute to test measurements is subtracted
from those measurements to produce the final timing num-
bers as published in the speed files and data sheet.
Using IBIS Models to Simulate Load
Conditions in Application
IBIS models permit the most accurate prediction of timing
delays for a given application. The parameters found in the
IBIS model (V_REF, R_REF, and V_MEAS) correspond directly
with the parameters used in Table 94 (V_T, R_T, and V_M). Do
not confuse V_REF (the termination voltage) from the IBIS
model with V_REF (the input-switching threshold) from the
table. A fourth parameter, C_REF, is always zero. The four
parameters describe all relevant output test conditions. IBIS
models are found in the Xilinx development software as well
as at the following link:
http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp
Delays for a given application are simulated according to its
specific load conditions as follows:
1. Simulate the desired signal standard with the output
driver connected to the test setup shown in Figure 73.
Use parameter values V_T, R_T, and V_M from Table 94.
C_REF is zero.
2. Record the time to V_M.
3. Simulate the same signal standard with the output
driver connected to the PCB trace with load. Use the
appropriate IBIS model (including V_REF, R_REF, C_REF,
and V_MEAS values) or capacitive value to represent the
load.
4. Record the time to V_MEAS.
5. Compare the results of steps 2 and 4. Add (or subtract)
the increase (or decrease) in delay to (or from) the
appropriate Output standard adjustment (Table 93) to
yield the worst-case delay of the PCB trace.
DS312-3 (v3.4) November 9, 2006
www.xilinx.com
135
Product Specification