XC3S100E_06 Datasheet, PDF (31/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

R
Functional Description
The MULT_AND is useful for small multipliers. Larger multi-
pliers can be built using the dedicated 18x18 multiplier
blocks (see Dedicated Multipliers).
Storage Elements
The storage element, which is programmable as either a
D-type flip-flop or a level-sensitive transparent latch, pro-
vides a means for synchronizing data to a clock signal,
among other uses. The storage elements in the top and bot-
tom portions of the slice are called FFY and FFX, respec-
tively. FFY has a fixed multiplexer on the D input selecting
either the combinatorial output Y or the bypass signal BY.
FFX selects between the combinatorial output X or the
bypass signal BX.
The functionality of a slice storage element is identical to
that described earlier for the I/O storage elements. All sig-
nals have programmable polarity; the default active-High
function is described.
Table 15: Storage Element Signals
Signal
Description
D
Input. For a flip-flop data on the D input is loaded when R and S (or CLR and PRE) are Low and CE is High
during the Low-to-High clock transition. For a latch, Q reflects the D input while the gate (G) input and gate
enable (GE) are High and R and S (or CLR and PRE) are Low. The data on the D input during the High-to-Low
gate transition is stored in the latch. The data on the Q output of the latch remains unchanged as long as G or
GE remains Low.
Q
Output. Toggles after the Low-to-High clock transition for a flip-flop and immediately for a latch.
C
Clock for edge-triggered flip-flops.
G
Gate for level-sensitive latches.
CE
Clock Enable for flip-flops.
GE
Gate Enable for latches.
S
Synchronous Set (Q = High). When the S input is High and R is Low, the flip-flop is set, output High, during the
Low-to-High clock (C) transition. A latch output is immediately set, output High.
R
Synchronous Reset (Q = Low); has precedence over Set.
PRE
Asynchronous Preset (Q = High). When the PRE input is High and CLR is Low, the flip-flop is set, output High,
during the Low-to-High clock (C) transition. A latch output is immediately set, output High.
CLR Asynchronous Clear (Q = Low); has precedence over Preset to reset Q output Low
SR
CLB input for R, S, CLR, or PRE
REV CLB input for opposite of SR. Must be asynchronous or synchronous to match SR.
The control inputs R, S, CE, and C are all shared between
the two flip-flops in a slice.
S
FDRSE
D
Q
CE
C
R
DS312-2_40_021305
Figure 25: FD Flip-Flop Component with Synchronous
Reset, Set, and Clock Enable
Table 16: FD Flip-Flop Functionality with Synchronous
Reset, Set, and Clock Enable
Inputs
Outputs
R
S CE D
C
Q
1
X
X
X↑
0
0
1
X
X↑
1
0
0
0
X
X
No Change
0
0
1
1
↑
1
0
0
1
0
↑
0
Initialization
The CLB storage elements are initialized at power-up, dur-
ing configuration, by the global GSR signal, and by the indi-
vidual SR or REV inputs to the CLB. The storage elements
can also be re-initialized using the GSR input on the
DS312-2 (v3.4) November 9, 2006
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Product Specification