XC3S100E_06 Datasheet, PDF (157/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

R
DC and Switching Characteristics
Table 119: Timing for Byte-wide Peripheral Interface (BPI) Configuration Mode (Continued)
Symbol
Description
Minimum Maximum
T_CCO
T_DCC
T_CCD
Address A[23:0] outputs valid after CCLK falling edge
Setup time on D[7:0] data inputs before CCLK falling edge
Hold time on D[7:0] data inputs after CCLK falling edge
See Table 115
See Table 115
See Table 115
Units
Table 120: Configuration Timing Requirements for Attached Parallel NOR Flash
Symbol
Description
Requirement
Units
T_CE
(t_ELQV)
Parallel NOR Flash PROM chip-select time
T_CE ≤ T_INITADDR
ns
T_OE
(t_GLQV)
Parallel NOR Flash PROM output-enable time
T_OE ≤ T_INITADDR
ns
T_ACC
(t_AVQV)
Parallel NOR Flash PROM read access time _{TACC ≤ TCCLKn(min) – TCCO – TDCC – PCB}
ns
T_BYTE
For x8/x16 PROMs only: BYTE# to output valid
ns
(t_FLQV,
time⁽³⁾
T_BYTE ≤ T_INITADDR
t_FHQV)
Notes:
1. These requirements are for successful FPGA configuration in BPI mode, where the FPGA provides the CCLK frequency. The post
configuration timing can be different to support the specific needs of the application loaded into the FPGA and the resulting clock source.
2. Subtract additional printed circuit board routing delay as required by the application.
3. The initial BYTE# timing can be extended using an external, appropriately sized pull-down resistor on the FPGA’s LDC2 pin. The resistor
value also depends on whether the FPGA’s HSWAP pin is High or Low.
Table 121: MultiBoot Trigger (MBT) Timing
Symbol
Description
T_MBT
MultiBoot Trigger (MBT) Low pulse width required to initiate
MultiBoot reconfiguration
Minimum
300
Maximum
∞
Notes:
1. MultiBoot re-configuration starts on the rising edge after MBT is Low for at least the prescribed minimum period.
Units
ns
DS312-3 (v3.4) November 9, 2006
www.xilinx.com
157
Product Specification