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XC3S100E_06 Datasheet, PDF (149/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)
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R
DC and Switching Characteristics
Configuration and JTAG Timing
General Configuration Power-On/Reconfigure Timing
VCCINT
1.2V
(Supply)
1.0V
VCCAUX
2.5V
(Supply)
2.0V
VCCO Bank 2
(Supply)
1.0V
PROG_B
(Input)
INIT_B
(Open-Drain)
CCLK
(Output)
TPOR
TPROG
TPL
TICCK
Notes:
DS312-3_01_103105
1. The VCCINT, VCCAUX, and VCCO supplies may be applied in any order.
2. The Low-going pulse on PROG_B is optional after power-on but necessary for reconfiguration without a power cycle.
3. The rising edge of INIT_B samples the voltage levels applied to the mode pins (M0 - M2).
Figure 74: Waveforms for Power-On and the Beginning of Configuration
Table 110: Power-On Timing and the Beginning of Configuration
Symbol
TPOR(2)
TPROG
TPL(2)
TINIT
TICCK(3)
Description
The time from the application of VCCINT, VCCAUX, and VCCO
Bank 2 supply voltage ramps (whichever occurs last) to the
rising transition of the INIT_B pin
The width of the low-going pulse on the PROG_B pin
The time from the rising edge of the PROG_B pin to the
rising transition on the INIT_B pin
Minimum Low pulse width on INIT_B output
The time from the rising edge of the INIT_B pin to the
generation of the configuration clock signal at the CCLK
output pin
Device
XC3S100E
XC3S250E
XC3S500E
XC3S1200E
XC3S1600E
All
XC3S100E
XC3S250E
XC3S500E
XC3S1200E
XC3S1600E
All
All
All Speed Grades
Min
Max
-
5
-
5
-
5
-
5
-
7
0.5
-
-
0.5
-
0.5
-
1
-
2
-
2
250
-
0.5
4.0
Units
ms
ms
ms
ms
ms
μs
ms
ms
ms
ms
ms
ns
μs
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 76. This means power must be applied to all VCCINT, VCCO,
and VCCAUX lines.
2. Power-on reset and the clearing of configuration memory occurs during this period.
3. This specification applies only to the Master Serial, SPI, BPI-Up, and BPI-Down modes.
DS312-3 (v3.4) November 9, 2006
www.xilinx.com
149
Product Specification
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